BK2425

Revision 1.0

Proprietary and Confidential

Page 14 of 30

Cn: SPI command bit

Sn: STATUS register bit

Dn: Data Bit (LSB byte to MSB byte, MSB bit in each byte first)

Note: The SPI timing is for bank 0 and register 9 to 14 at bank 1. For register 0 to 8 at bank 1, the byte

order is inversed that the MSB byte is R/W before LSB byte.

Figure 7 SPI NOP timing diagram

Symbol

Parameters

Min

Max

Units

Tdc

Data to SCK Setup

10

ns

Tdh

SCK to Data Hold

20

ns

Tcsd

CSN to Data Valid

38

ns

Tcd

SCK to Data Valid

55

ns

Tcl

SCK Low Time

40

ns

Tch

SCK High Time

40

ns

Fsck

SCK Frequency

0

8

MHz

Tr,Tf

SCK Rise and Fall

100

ns

Tcc

CSN to SCK Setup

2

ns

Tcch

SCK to CSN Hold

2

ns

Tcwh

CSN Inactive time

50

ns

Tcdz

CSN to Output High Z

38

ns

Table 3 SPI timing parameter