Everest Semiconductor

Confidential

ES7243

Revision 10.0

5

March 2019

Latest datasheet: www.everest-semi.com or info@everest-semi.com

Chip Address

R/W

Register Address

Start

0010 0 ̴AD1 ̴AD0

0

ACK

RAM

ACK

Chip Address

R/W

Data to be read

Start

0010 0 ̴AD1 ̴AD0

1

ACK

Data

NACK

Stop

5. DIGITAL AUDIO INTERFACE

The device provides many formats of serial audio data interface to the output from the ADC

ADC data is out at SDOUT on the falling edge of SCLK. The relationships of SDOUT (SDATA), SCLK

and LRCK with these formats are shown through Figure 2 to Figure 5. The device supports up to

8-ch of TDM, please refer to user guide for detail description.

n-2 n-1

n

3

2

1

1 SCLK

MSB

LSB

LEFT CHANNEL

n-2 n-1

n

3

2

1

1 SCLK

MSB

LSB

RIGHT CHANNEL

SDATA

SCLK

LRCK

STOP

ACK

ACK

Write ACK

Chip Addr

START

bit 1 to 7

bit 1 to 8

Reg Addr

bit 1 to 8

Write Data

CCLK

CDATA

STOP

ACK

Write ACK

Chip Addr

START

bit 1 to 7

bit 1 to 8

Reg Addr

bit 1 to 8

Read Data

START

Read ACK

Chip Addr

bit 1 to 7

NO ACK

CCLK

CDATA