RF96 datasheet(60/121 Pages) HOPE

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Page 60

RF96/97/98

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WIRELESS & SENSING

PRELIMINARY

DATASHEET

4.2.9. Data Processing in FSK/OOK Mode

4.2.9.1. Block Diagram

Figure below illustrates the RF96/97/98 data processing circuit. Its role is to interface the data to/from the modulator/

demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers.

The circuit contains several control blocks which are described in the following paragraphs.

Tx/Rx

CONTROL

DIO0

DIO1

DIO2

DIO3

DIO4

DIO5

Data

SYNC

RECOG.

PACKET

HANDLER

FIFO

(+SR)

SPI

NSS

SCK

MOSI

MISO

Potential datapaths (data operation mode dependant)

Figure 25. RF96/97/98 Data Processing Conceptual View

The RF96/97/98 implements several data operation modes, each with their own data path through the data processing

section. Depending on the data operation mode selected, some control blocks are active whilst others remain disabled.

4.2.9.2. Data Operation Modes

The RF96/97/98 has two different data operation modes selectable by the user:

 Continuous mode: each bit transmitted or received is accessed in real time at the DIO2/DATA pin. This mode may be

used if adequate external signal processing is available.

 Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The packet is automatically

built with preamble, Sync word, and optional CRC and DC-free encoding schemes The reverse operation is performed

in reception. The uC processing overhead is hence significantly reduced compared to Continuous mode. Depending on

the optional features activated (CRC, etc) the maximum payload length is limited to 255, 2047 bytes or unlimited.

Each of these data operation modes is fully described in the following sections.

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