PD780C datasheet(6/24 Pages) NEC

6 / 24 page

I-'PD780

NEe

AC Characteristics

TA =

OOC to +70oC; vee

+5 V ± 5%; unless otherwise specified

Limits

�P07ao (2.5 MHz)

1"0780-1{4 MHz)

1'.0780-2 II MHz)

11151

Parameter

Symbol

Min

Max

Min

Max

Unit

Condlltons

Clock period

0.4

(1)

0.25

(I )

0.165

)

I's

Clock pulse width, clock high

tw(+H)

180

(2)

110

(2)

Clock pulse width, clock low

tw(+L)

180

2000

110

2000

Clock rise and fall time

tRf

Address output delay

145

110

Delay to float

tF(AD)

110

Address stable prior to MREO (Memory cycle)

tACM

(3)

ns CL

Address stable prior to lORa, RD or WR (1/0 cycle)

tACI

(4)

Address stable from RD or WR

tCA

(5)

Address stable from RD or WR during Float

tCAF

(6)

Data output delay

230

150

130

Delay to float during write cycle

Data setup time to rising edge of clock during Ml cycle ts,(O)

Data setup time to falling edge of clock during M2

to M5 cycles

ts,(O)

ns CL

200

Data stable prior to WR (Memory cycle)

tDCM

(7)

Data stable prior to WR (1/0 cycle)

tOCI

(8)

Data stable from WR

tCOF

(9)

BUSRO setup time to rising edge of clock

BUSAK delay from rising edge of clock to BUSAK low

tOL(BA)

t20

100

BUSAK delay from falling edge of clock to BUSAK high to

110

100

ns CL =50 pF

Delay to float (MREO, lORa, RD and WR)

tF(C)

100

Ml stable prior to 10RO (Interrupt ack.)

tMR

(10)

Any hold time for setup time

HALT delay lime from falling edge of clock

300

260

ns CL = 50 pF

1NT setup time to rising edge of clock

10RO delay from rising edge of clock to 10RO low

10RO delay from falling edge of clock to 10RO low

110

10RO delay from rising edge of clock to 10RO high

100

10RO delay from falling edge of clock to lORa high

tOH+(IR)

110

ns CL=50pF

Ml delay from rising edge of clock to Ml low

130

100

Ml delay from rising edge of clock to Ml high

130

100

MREQ delay from falling edge of clock to MREO low

100

MREO delay from rising edge of clock to MREO high

100

MREO delay from falling edge of clock to MREO high

100

Pulse width, MREO low

(11

)

(11)

Pulse width, MREO high

(12)

Pulse width, NMI low

RESET setup time to rising edge of clock

RD delay from rising edge of clock to RD low

100

RD delay from falling edge of clock to RD low

130

RD delay from rising edge of clock 10 RD high

100

RiJ

delay from falling edge of clock to RD high

tOH,(RO)

110

ns CL

30pF

4-8

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