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PD780C датащи(PDF) 3 Page - NEC

номер детали PD780C
подробное описание детали  HIGH·PERFORMANCE CP/M® ·COMPATIBLE NMOS 8·BIT MICROPROCESSOR
PDF  24 Pages
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производитель  NEC [NEC]
домашняя страница  http://www.nec.com/
Logo NEC - NEC

PD780C датащи(HTML) 3 Page - NEC

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ttiEC
RD (Read)
This three-state active low output is used to strobe
data from external memory or 1/0 devices onto the data
bus. RD is asserted to indicate the CPU is requesting
data from external memory or 1/0 devices. This line is
three-stated during halt or reset conditions.
MREQ (Memory Request)
This three-state active low output is used to indicate
that the address specified for the memory read or write
is valid.
M1 (Machine Cycle 1)
This active low output is used to indicate that the cur­
rent machine cycle is the opcode fetch phase of an
instruction execution.
HALT (Halt State)
This active low input is used with the HALT instruc­
tion to initiate a halt state. When HALT is asserted, pro­
gram execution stops and does not resume until an in­
terrupt is generated. During the halt state, NOPs are
executed in order to continue memory refresh
operations.
WAIT (Wait State)
This active low input is used to indicate that the ex­
ternal memory or 1/0 devices addressed by the CPU
are not ready to transfer data. When WAIT is asserted,
the CPU is placed in a wait condition.
�PD780
RESET
This active low input signal is used to initialize the
CPU. When RESET is asserted, the interrupt enable flip
flop is reset, the program counter and the
I and R
registers are cleared, and interrupt response mode 0
is enabled. In a reset condition, the address and data
busses are three-stated and all output control signals
are inactive, after which program execution begins
from address 0000.
The pulse width of RESET must be a minimum of 3
clock cycles in length to reinitialize the CPU and
stabilize operation.
RFSH (Refresh)
This active low output is used in conjunction with the
MREQ signal to initiate a refresh read of all external
dynamic memory. RFSH and MREQ are both asserted
when the least significant 7 bits of the address on the
address bus hold a valid external dynamic memory
address.
� (Clock)
This line is an input for external clock sources.
+5 V
Single +5 V power supply.
GND
Ground.
4-5



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