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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F030R8 датащи(PDF) 70 Page - STMicroelectronics |
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STM32F030R8 датащи(HTML) 70 Page - STMicroelectronics |
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70 / 93 page  Electrical characteristics STM32F030x4/x6/x8/xC 70/93 DS9773 Rev 4 Figure 23. ADC accuracy characteristics Figure 24. Typical connection diagram using the ADC 1. Refer to Table 50: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 13: Power supply scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. ET = total unajusted error: maximum deviation between the actual and ideal transfer curves. EO = offset error: maximum deviation between the first actual transition and the first ideal one. EG = gain error: deviation between the last ideal transition and the last actual one. ED = differential linearity error: maximum deviation between actual steps and the ideal ones. EL = integral linearity error: maximum deviation between any actual transition and the end point correlation line. (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4095 4094 4093 7 6 5 4 3 2 1 0 23 4 5 6 1 7 4093 4094 4095 4096 VDDA VSSA EO ET EL EG ED 1 LSB IDEAL (1) (3) (2) MS19880V2 MS33900V1 VDDA AINx IL±1 μA VT RAIN (1) Cparasitic VAIN VT RADC 12-bit con ver ter CADC Sample and hold ADC con ver ter |
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