AD5380 datasheet(30/34 Pages) AD

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PRELIMINARY TECHNICAL DATA

REV. PrF 09/2003

–30–

AD5380

AD5380 to 8051

The AD5380 requires a clock synchronized to the serial

data. The 8051 serial interface must therefore be operated

in Mode 0. In this mode serial data enters and exits

through RxD and a shift clock is output on TxD. Figure

17 shows how the 8051 is connected to the AD5380. Be-

cause the AD5380 shifts data out on the rising edge of

the shift clock and latches data in on the falling edge,

the shift clock must be inverted. The AD5380 requires

its data with the MSB first. Since the 8051 outputs the

LSB first, the transmit routine must take this into account.

AD5380 to ADSP2101/2103

Figure 18 shows a serial interface between the AD5380

and the ADSP-2101/ADSP-2103. The ADSP-2101/

ADSP-2103 should be set up to operate in the SPORT

Transmit Alternate Framing Mode. The ADSP-2101/

ADSP-2103 SPORT is programmed through the SPORT

control register and should be configured as follows: Inter-

nal Clock Operation, Active Low Framing, 16-Bit Word

Length. Transmission is initiated by writing a word to the

Tx register after the SPORT has been enabled.

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consid-

eration of the power supply and ground return layout

helps to ensure the rated performance. The printed circuit

board on which the AD5380 is mounted should be de-

signed so that the analog and digital sections are

separated, and confined to certain areas of the board. If

the AD5380 is in a system where multiple devices require

an AGND-to-DGND connection, the connection should

be made at one point only. The star ground point

should be established as close as possible to the device.

For supplies with multiple pins (AVDD, AVCC) it is recom-

mended to tie those pins together. The AD5380 should

have ample supply bypassing of 10 µF in parallel with

0.1 µF on each supply located as close to the package as

possible, ideally right up against the device. The 10 µF

capacitors are the tantalum bead type. The 0.1 µF capacitor

should have low Effective Series Resistance (ESR) and Ef-

fective Series Inductance (ESI), like the common

ceramic types that provide a low impedance path to

ground at high frequencies, to handle transient currents

due to internal logic switching.

The power supply lines of the AD5380 should use as large a

trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line. Fast

switching signals such as clocks should be shielded with

digital ground to avoid radiating noise to other parts of

the board, and should never be run near the reference

inputs. A ground line routed between the DIN and SCLK

lines will help reduce crosstalk between them (not required

on a multilayer board as there will be a separate ground

plane, but separating the lines will help). It is essential to

minimize noise on VIN and REFIN lines.

Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to

each other. This reduces the effects of feedthrough through

the board. A microstrip technique is by far the best, but not

always possible with a double-sided board. In this tech-

nique, the component side of the board is dedicated to

ground plane while signal traces are placed on the solder

side.

SCK

ADSP2101/

ADSP2103

RESET

SCLK

SDO

DIN

SYNC

AD538X

DVDD

SPI/I2C

RFS

SER/PAR

TFS

Figure 18 . AD5380 -ADSP2101/ADSP3103 Interface

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