PRELIMINARY TECHNICAL DATA

REV. PrF 09/2003

–12–

AD5380

VOUT39/MON_OUT

This pin has a dual function, it acts a a buffered output for channel 39 in default mode but

when the monitor function is enabled this output acts as the output of a 39-to-1 channel

multiplexer which can be programmed to multiplex one of channels 0 to 38 to the

MON_OUT pin. The MON_OUT pins output impedance is typically 500 ohms and is

intended to drive a high input impedance like that exhibited by SAR ADC inputs.

SER/

PAR.

Interface Select Input. This pin allows the user to select whether the serial or parallel

interface will be used. If it is tied high the serial interface mode is selected and pin 97 (

SPI/

I2C) is used to determine if the interface mode is SPI or I2C.

Parallel interface mode is selected when SER/

PAR is low.

CS/(SYNC/AD0)

In parallel interface mode this pin acts as Chip Select Input (level sensitive, active low).

When low the AD5380 device is selected.

Serial Interface Mode: This is the Frame Synchronisation input signal for the serial

interface. When taken low the internal counter is enabled to count the required number of

clocks before the addressed register is updated.

I2C Mode: This pin acts as a hardware address pin used in conjunction with AD1 to

determine the software address for the device on the I2C bus.

WR /(DCEN/AD1)

Multi Function pin. In parallel interface mode acts as Write enable and in serial interface

mode acts as a daisy chain enable in SPI mode and as a hardware address pin in I2C mode.

Parallel Interface Write Input (edge sensitive). The rising edge of

WR is used in conjunction

with

CS low and the address bus inputs to write to the selected device registers.

Serial Interface: Daisy-Chain Select Input (level sensitive, active high). When high this

signal is used in conjunction with SER/

PAR high to enable SPI serial interface daisy-chain

mode.

I2C Mode: This pin acts as a hardware address pin used in conjunction with AD0 to

determine the software address for this device on the I2C bus.

DB13-DB0

Parallel Data Bus. DB13 is the MSB and DB0 is the LSB of the input data word on the

AD5380

A5-A0

Parallel Address Inputs. A5 to A0 are decoded to address one of the 40 input channels on the

AD5380. Used in conjunction with the REG1 and REG0 pins to determine the destination

register for the input data.

REG1,REG0

REG1 and REG0 are used in decoding the destination registers for the input data. REG1

and REG0 are decoded to address the input data register, offset register or gain register for

the selected channel and also are used to decide the special function registers.

SDOUT/(

A/B)

Serial Data Output in serial interface mode. Tristatable CMOS output. SDO can be used

for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising

edge of SCLK and is valid on the falling edge of SCLK.

When operating in parallel interface mode this pin acts as the A or B data register select

when writing data to the AD5380 data registers when toggle mode is selected (See Toggle

Mode Function). In toggle mode the LDAC is used to switch the output between the data

contained in the A and B data registers. All DAC channels contain two data registers. In

normal mode data register A is the default for data transfers.

BUSY

Digital CMOS Output.

BUSY goes low during internal calculations of the data (x2) loaded

to the DAC data register. During this time the user can continue writing new data to further

x1, c and m registers (these are stored in a FIFO) but no further updates to the DAC

registers and DAC outputs can take place. If

LDAC is taken low while

BUSY is low this

event is stored.

BUSY also goes low during power-on-reset and when the RESET pin is

low. During this time the interface is disabled and any events on

LDAC are ignored. A

CLR operation also brings

BUSY low.

LDAC

Load DAC Logic Input (active low). If

LDAC is taken low while BUSY is inactive (high)

the contents of the input registers are transferred to the DAC registers and the DAC outputs

are updated. If

LDAC is taken low while BUSY is active and internal calculations are

taking place, the

LDAC event is stored and the DAC registers are updated when BUSY

goes inactive. However any events on

LDAC during power-on-reset or RESET are ignored.

CLR

Asynchronous Clear Input (level sensitive, active low). While

CLR is low all LDAC pulses

are ignored. When

CLR is activated all channels are updated with the data contained in the

CLR code register. BUSY is low for a duration of 12us while all channels are being

updated with the

CLR code.

RESET

Asynchronous Digital Reset Input (falling edge sensitive). The function of this pin is

equivalent to that of the Power-On-Reset generator. When this pin is taken low, the state-

machine initiates a reset sequence to digitally reset x1, m, c, and x2 registers to their default