LTC2436-1IGN datasheet(21/28 Pages) LINER

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LTC2436-1

24361f

by Figures 14 and 15. For simplicity, two distinct situa-

tions can be considered.

For relatively small values of input capacitance (CIN <

0.01

µF), the voltage on the sampling capacitor settles

almost completely and relatively large values for the

source impedance result in only small errors. Such values

for CIN will deteriorate the converter offset and gain

performance without significant benefits of signal filtering

and the user is advised to avoid them. Nevertheless, when

small values of CIN are unavoidably present as parasitics

of input multiplexers, wires, connectors or sensors, the

LTC2436-1 can maintain its accuracy while operating with

relative large values of source resistance as shown in

Figure 16. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)

Figure 17. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)

APPLICATIO S I FOR ATIO

RSOURCE (Ω)

0 100 200 300 400 500 600 700 800 900 1000

24361 F16

VCC = 5V

REF+ = 5V

REF – = GND

IN+ = 3.75V

IN– = 1.25V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0.1µF

CIN = 1µF, 10µF

RSOURCE (Ω)

0 100 200 300 400 500 600 700 800 900 1000

24361 F17

–4

–8

–12

–16

–20

VCC = 5V

REF+ = 5V

REF – = GND

IN+ = 1.25V

IN– = 3.75V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0.1µF

CIN = 1µF, 10µF

Figure 15. –FS Error vs RSOURCE at IN

+ or IN– (Small CIN)

RSOURCE (Ω)

100

10k

100k

24361 F15

–3

–2

–1

VCC = 5V

REF+ = 5V

REF – = GND

IN+ = GND

IN– = 2.5V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0.001µF

CIN = 100pF

CIN = 0pF

Figures 14 and 15. These measured results may be slightly

different from the first order approximation suggested

earlier because they include the effect of the actual second

order input network together with the nonlinear settling

process of the input amplifiers. For small CIN values, the

settling on IN+ and IN– occurs almost independently and

there is little benefit in trying to match the source imped-

ance for the two pins.

Larger values of input capacitors (CIN > 0.01µF) may be

required in certain configurations for antialiasing or gen-

eral input signal filtering. Such capacitors will average the

input sampling charge and the external source resistance

will see a quasi constant input differential impedance.

When FO = LOW (internal oscillator and 50Hz/60Hz notch),

the typical differential input resistance is 2M

Ω which will

generate a gain error of approximately 1LSB at full scale

for each 60

Ω of source resistance driving IN+ or IN–.

When FO is driven by an external oscillator with a fre-

quency fEOSC (external conversion clock operation), the

typical differential input resistance is 0.28 • 1012/fEOSCΩ

and each ohm of source resistance driving IN+ or IN– will

result in 1.11 • 10–7 • fEOSCLSB gain error at full scale. The

effect of the source resistance on the two input pins is

additive with respect to this gain error. The typical +FS and

–FS errors as a function of the sum of the source resis-

tance seen by IN+ and IN– for large values of CIN are shown

in Figures 16 and 17.

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