LTC2436-1IGN datasheet(13/28 Pages) LINER

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LTC2436-1

24361f

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer has

been completed. The LTC2436-1 will abort any serial data

transfer in progress and start a new conversion cycle

anytime a LOW-to-HIGH transition is detected at the CS

pin after the converter has entered the data output state

(i.e., after the first rising edge of SCK occurs with

CS = LOW).

Finally, CS can be used to control the free-running modes

of operation, see Serial Interface Timing Modes section.

Grounding CS will force the ADC to continuously convert

at the maximum output rate selected by FO.

SERIAL INTERFACE TIMING MODES

The LTC2436-1’s 3-wire interface is SPI and MICROWIRE

compatible. This interface offers several flexible modes of

operation. These include internal/external serial clock,

2- or 3-wire I/O, single cycle conversion and autostart. The

following sections describe each of these serial interface

timing modes in detail. In all these cases, the converter

can use the internal oscillator (FO = LOW) or an external

oscillator connected to the FO pin. Refer to Table 4 for a

summary.

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 6.

The serial clock mode is selected on the falling edge of CS.

To select the external serial clock mode, the serial clock pin

(SCK) must be LOW during each CS falling edge.

Figure 6. External Serial Clock, Single Cycle Operation

Table 4. LTC2436-1 Interface Timing Modes

Conversion

Data

Connection

SCK

Cycle

Output

and

Configuration

Source

Control

Waveforms

External SCK, Single Cycle Conversion

External

CS and SCK

Figures 6, 7

External SCK, 2-Wire I/O

External

SCK

Figure 8

Internal SCK, Single Cycle Conversion

Internal

↓

Figures 9, 10

Internal SCK, 2-Wire I/O, Continuous Conversion

Internal

Continuous

Internal

Figure 11

EOC

BIT 18

SDO

SCK

(EXTERNAL)

TEST EOC

MSB

SIG

CH0/CH1

BIT 0

LSB

BIT 2

BIT 1

BIT 14

BIT 13

BIT 15

BIT 16

BIT 17

SLEEP

TEST EOC

(OPTIONAL)

DATA OUTPUT

CONVERSION

24361 F06

CONVERSION

Hi-Z

TEST EOC

VCC

REF+

SCK

CH1+

CH1–

SDO

GND

114

8, 9, 10, 15, 16

REFERENCE

VOLTAGE

0.1V TO VCC

CH0+

CH0–

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

µF

2.7V TO 5.5V

LTC2436-1

3-WIRE

SPI INTERFACE

REF–

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/SIMULTANEOUS

50Hz/60Hz REJECTION

APPLICATIO S I FOR ATIO

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