11

LTC2605/LTC2615/LTC2625

2605f

OPERATIO

Acknowledge

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the latest

byte of information was received. The Acknowledge

related clock pulse is generated by the master. The master

releases the SDA line (HIGH) during the Acknowledge

clock pulse. The slave-receiver must pull down the SDA

during the Acknowledge clock pulse so that it remains a

stable LOW during the HIGH period of this clock pulse. The

LTC2605/LTC2615/LTC2625 respond to a write by a mas-

ter in this manner. The LTC2605/LTC2615/LTC2625 do

not acknowledge a read (it retains SDA HIGH during the

period of the Acknowledge clock pulse).

Chip Address

The state of CA0, CA1 and CA2 decides the slave address

of the part. The pins CA0, CA1 and CA2 can be each set to

in 27 selectable addresses for the part. The addresses

corresponding to the states of CA0, CA1 and CA2 and the

global address are shown in Table 2.

In addition to the address selected by the address pins, the

parts also respond to a global address. This address allows

a common write to all LTC2605, LTC2615 and LTC2625

parts to be accomplished with one 3-byte write transaction

address and is not selectable by CA0, CA1 and CA2. The

maximum capacitive load allowed on the address pins

(CA0, CA1 and CA2) is 10pF.

Write Word Protocol

The master initiates communication with the LTC2605/

LTC2615/LTC2625 with a START condition and a 7-bit

slave address followed by the Write bit (W) = 0. The

LTC2605/LTC2615/LTC2625 acknowledges by pulling the

SDA pin low at the 9th clock if the 7-bit slave address

matches the address of the parts (set by CA0, CA1 and

CA2) or the global address. The master then transmits

three bytes of data. The LTC2605/LTC2615/LTC2625

acknowledges each byte of data by pulling the SDA line low

at the 9th clock of each data byte transmission. After

receiving three complete bytes of data, the LTC2605/

LTC2615/LTC2625 executes the command specified in

the 24-bit input word.

If more than three data bytes are transmitted after a valid

7-bit slave address, the LTC2605/LTC2615/LTC2625 do

not acknowledge the extra bytes of data (SDA is high

during the 9th clock).

The format of the three data bytes is shown in Figure 2. The first

byte of the input word consists of the 4-bit command and 4-

bit DAC address. The next two bytes consist of the 16-bit data

word. The 16-bit data word consists of the 16-, 14- or 12-bit

input code, MSB to LSB, followed by 0, 2 or 4 don’t care bits

write transaction is shown in Figure 3.

S

INPUT WORD

WRITE WORD PROTOCOL FOR LTC2605/LTC2615/LTC2625

INPUT WORD (LTC2605)

SLAVE ADDRESS

W

A

A

1ST DATA BYTE

2ND DATA BYTE

A

3RD DATA BYTE

AP

2605/2615/2625 O01

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

C3

C2

C1

C0

A3

A2

A1

A0

D13

D14

D15

D12 D11 D10 D9

D8

D7 D6

D5

D4

D3

D2

D1 D0

INPUT WORD (LTC2615)

C3

C2

C1

C0

A3

A2

A1

A0

D11

D12

D13

D10 D9

D8

D7

D6

D5 D4

D3

D2

D1

D0

X

X

INPUT WORD (LTC2625)

C3

C2

C1

C0

A3

A2

A1

A0

D9

D10

D11

D8

D7

D6

D5

D4

D3 D2

D1

D0

X

X

X

X

Figure 2