10

LTC2605/LTC2615/LTC2625

2605f

Table 1.

COMMAND*

C3

C2

C1

C0

0000

Write to Input Register n

0001

Update (Power Up) DAC Register n

0010

Write to Input Register n, Update (Power Up) All n

0011

Write to and Update (Power Up) n

0100

Power Down n

1111

No Operation

*Address and command codes not shown are reserved and should not be used.

ADDRESS (n)*

A3

A2

A1

A0

0000

DAC A

0001

DAC B

0010

DAC C

0011

DAC D

0100

DAC E

0101

DAC F

0110

DAC G

0111

DAC H

1111

All DACs

where k is the decimal equivalent of the binary DAC input

(Pin 6).

Serial Digital Interface

The LTC2605/LTC2615/LTC2625 communicate with a

host using the standard 2-wire digital interface. The

Timing Diagram (Figure 1) shows the timing relationship

of the signals on the bus. The two bus lines, SDA and SCL,

must be high when the bus is not in use. External pull-up

resistors or current sources are required on these lines.

The value of these pull-up resistors is dependent on the

pull-up will be necessary if the bus capacitance is greater

than 200pF.

The LTC2605/LTC2615/LTC2625 are receive-only (slave)

devices. The master can write to the LTC2605/LTC2615/

LTC2625. The LTC2605/LTC2615/LTC2625 do not

respond to a read from the master.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition.

A START condition is generated by transitioning SDA from

high to low while SCL is high.

When the master has finished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from low to high while SCL

is high. The bus is then free for communication with

OPERATIO

Power-On Reset

The LTC2605/LTC2615/LTC2625 clear the outputs to

zero scale when power is first applied, making system

initialization consistent and repeatable. The LTC2605-1/

LTC2615-1/LTC2625-1 set the voltage outputs to midscale

when power is first applied.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2605/

LTC2615/LTC2625 contain circuitry to reduce the

power-on glitch: the analog outputs typically rise less

than 10mV above zero scale during power on if the

power supply is ramped to 5V in 1ms or more. In general,

the glitch amplitude decreases as the power supply ramp

time is increased. See Power-On Reset Glitch in the

Typical Performance Characteristics section.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range

– 0.3V

Ratings). Particular care should be taken to observe these

limits during power supply turn-on and turn-off sequences,

Transfer Function

The digital-to-analog transfer function is

V

k

V

OUT IDEAL

N

REF

⎛

⎝⎜

⎞

⎠⎟

2