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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DAC8420FSZ датащи(PDF) 8 Page - Analog Devices |
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DAC8420FSZ датащи(HTML) 8 Page - Analog Devices |
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8 / 23 page  DAC8420 Data Sheet Rev. C | Page 8 of 23 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 VOUTD 2 VOUTC 3 VREFLO 4 CLSEL 16 CLR 15 LD 14 NC 13 VREFHI 5 VOUTB 6 VOUTA 7 CS 12 CLK 11 SDI 10 VSS 8 GND 9 NC = NO CONNECT DAC8420 TOP VIEW (Not to Scale) Figure 4. PDIP and CERDIP VDD 1 VOUTD 2 VOUTC 3 VREFLO 4 CLSEL 16 CLR 15 LD 14 NC 13 VREFHI 5 CS 12 VOUTB 6 CLK 11 VOUTA 7 SDI 10 VSS 8 GND 9 NC = NO CONNECT DAC8420 TOP VIEW (Not to Scale) Figure 5. SOIC Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Positive Power Supply, 5 V to 15 V. 4 VREFLO Reference Input. Lower DAC ladder reference voltage input, equal to zero-scale output. Allowable range is VSS to (VVREFHI − 2.5 V). 5 VREFHI Reference Input. Upper DAC ladder reference voltage input. Allowable range is (VDD − 2.5 V) to (VVREFLO + 2.5 V). 7, 6, 3, 2 VOUTA through VOUTD Buffered DAC Analog Voltage Outputs. 8 VSS Negative Power Supply, 0 V to −15 V. 9 GND Power Supply, Digital Ground. 10 SDI Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register, which shifts data in, beginning with DAC Address Bit A1. This input is ignored when CS is high. SDI is CMOS/TTL compatible. The format of the 16-bit serial word is shown in Table 8. 11 CLK System Serial Data Clock Input, TTL/CMOS Levels. Data presented to the input SDI is shifted into the internal serial-parallel input register on the rising edge of clock. This input is logically OR’ed with CS. 12 CS Control Input, Device Chip Select, Active Low. This input is logically OR’ed with the clock and disables the serial data register input when high. When low, data input clocking is enabled (see Table 6). CS is CMOS/TTL compatible. 13 NC No Connect = Don’t Care. 14 LD Control Input, Asynchronous DAC Register Load Control, Active Low. The data currently contained in the serial input shift register is shifted out to the DAC data registers on the falling edge of LD, independent of CS. Input data must remain stable while LD is low. LD is CMOS/TTL compatible. 15 CLR Control Input, Asynchronous Clear, Active Low. Sets internal data Register A through Register D to zero or midscale, depending on current state of CLSEL. The data in the serial input shift register is unaffected by this control. CLR is CMOS/TTL compatible. 16 CLSEL Control Input, Determines action of CLR. If high, a clear command sets the internal DAC Register A through Register D to midscale (0x800). If low, the registers are set to zero (0x000). CLSEL is CMOS/ TTL compatible. Table 6. Control Function Logic Table CLK1 CS1 LD CLR CLSEL Serial Input Shift Register DAC Register A to DAC Register D NC2 High High Low High No change Loads midscale value (0x800) NC2 High High Low Low No change Loads zero-scale value (0x000) NC2 High High ↑ High /Low No change Latches value ↑ Low High High NC2 Shifts register one bit No change Low ↑ High High NC2 Shifts register one bit No change High NC ( ↑)2 ↓ High NC2 No change Loads the serial data-word3 High NC2 Low High NC2 No change Transparent4 NC2 High High High NC2 No change No change 1 CLK and CS are interchangeable. 2 NC = Don’t Care. 3 Returning CS high while CLK is high avoids an additional false clock of serial input data. CLK and CS are interchangeable. 4 Do not clock in serial data while LD is low. |
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