10 / 13 page
Rev. 1.0
10
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE1 = VIL and CE2=VIH.
3. Address valid prior to or coincident with /CE1 transition low and /or CE2 transition high.
4. /OE = VIL.
5.
Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
AC ELECTRICAL CHARACTERISTICS ( 0℃~70℃；Vcc=5V )
< WRITE CYCLE >
-70
JEDEC
Name
Symbol
Description
MIN
MAX
Unit
tAVAX
tWC
Write Cycle Time
70
ns
tE1LWH
tCW
Chip Select to End of Write
70
ns
tAVWL
tAS
Address Setup Time
0
ns
tAVWH
tAW
Address Valid to End of Write
70
ns
tWLWH
tWP
Write Pulse Width
50
ns
tWHAX
tWR
Write Recovery Time
0
ns
tWLQZ
tWHZ(10)
Write to Output in High Z
35
ns
tDVWH
tDW
Data to Write Time Overlap
40
ns
tWHDX
tDH
Data Hold for Write End
0
ns
tGHQZ
tOHZ(10)
Output Disable to Output in High Z
0
30
ns
tWHOX
tOW(10)
End of Write to Output Active
5
ns
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264
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