AD5686R datasheet(24/31 Pages) AD

24 / 31 page

AD5686R/AD5685R/AD5684R

Data Sheet

Rev. D | Page 24 of 31

POWER-DOWN OPERATION

The AD5686R/AD5685R/AD5684R contain three separate

power-down modes. Command 0100 is designated for the power-

down function (see Table 8). These power-down modes are

software-programmable by setting eight bits, Bit DB7 to Bit DB0,

in the input shift register. There are two bits associated with each

DAC channel. Table 11 shows how the state of the two bits

corresponds to the mode of operation of the device.

Table 11. Modes of Operation

Operating Mode

PDx1

PDx0

Normal Operation

Power-Down Modes

1 kΩ to GND

100 kΩ to GND

Three-State

Any or all DACs (DAC A to DAC D) can be powered down to

the selected mode by setting the corresponding bits. See

Table 12 for the contents of the input shift register during the

power-down/power-up operation.

When both Bit PDx1 and Bit PDx0 (where x is the channel

selected) in the input shift register are set to 0, the parts work

normally with its normal power consumption of 4 mA at 5 V.

However, for the three power-down modes, the supply current

falls to 4 μA at 5 V. Not only does the supply current fall, but the

output stage is also internally switched from the output of the

amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different

power-down options. The output is connected internally to

GND through either a 1 kΩ or a 100 kΩ resistor, or it is left

open-circuited (three-state). The output stage is illustrated in

Figure 54.

Figure 54. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are shut down when the power-down

mode is activated. However, the contents of the DAC register

are unaffected when in power-down. The DAC register can be

updated while the device is in power-down mode. The time

required to exit power-down is typically 4.5 μs for VDD = 5 V.

To reduce the current consumption further, the on-chip reference

can be powered off. See the Internal Reference Setup section.

Table 12. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation1

DB23

DB22

DB21

DB20

DB19 to DB16

DB15

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

(LSB)

PDD1

PDD0

PDC1

PDC0

PDB1

PDB0

PDA1

PDA0

Command bits (C3 to C0)

Address bits

Don’t care

Power-Down

Select DAC D

Power-Down

Select DAC C

Power-Down

Select DAC B

Power-Down

Select DAC A

1 X means don’t care.

RESISTOR

NETWORK

VOUTX

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

AD5686R датащи(PDF) 24 Page - Analog Devices

AD5686R датащи(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

датащи скачать

ссылки URL