AD5686R datasheet(21/31 Pages) AD

21 / 31 page

Data Sheet

AD5686R/AD5685R/AD5684R

Rev. D | Page 21 of 31

22B

SERIAL INTERFACE

The AD5686R/AD5685R/AD5684R have a 3-wire serial

interface (

SYNCE

, SCLK, and SDIN) that is compatible with

SPI, QSPI, and MICROWIRE interface standards as well as

most DSPs. See Figure 2 for a timing diagram of a typical

write sequence. The AD5686R/AD5685R/AD5684R contain

an SDO pin to allow the user to daisy-chain multiple devices

together (see the Daisy-Chain Operation section) or for

readback.

45B

Input Shift Register

The input shift register of the AD5686R/AD5685R/AD5684R is

24 bits wide. Data is loaded MSB first (DB23) and the first four

bits are the command bits, C3 to C0 (see Table 8), followed by

the 4-bit DAC address bits, DAC A, DAC B, DAC C, DAC D

(see Table 9), and finally the bit data-word.

The data-word comprises 16-bit, 14-bit, or 12-bit input code,

followed by zero, two or four don’t care bits for the AD5686R,

AD5685R, and AD5684R, respectively (see Figure 50, Figure 51,

and Figure 52). These data bits are transferred to the input

rising edge of

SYNCE

Commands can be executed on individual DAC channels,

combined DAC channels, or on all DACs, depending on the

address bits selected.

Table 8. Command Definitions

Command

Description

No operation

Write to Input Register n (dependent on

LDACE

)

Update DAC Register n with contents of Input

Write to and update DAC Channel n

Power down/power up DAC

Hardware

LDACE

mask register

Software reset (power-on reset)

Internal reference setup register

Set up DCEN register (daisy-chain enable)

Set up readback register (readback enable)

Reserved

…

Reserved

No operation, daisy-chain mode

Table 9. Address Commands

Address (n)

Selected DAC Channel

18F

DAC D

DAC C

DAC B

DAC A

DAC B

DAC C

DAC D

DAC A and DAC B

All DACs

Any combination of DAC channels can be selected using the address bits.

Figure 50. AD5686R Input Shift Register Content

Figure 51. AD5685R Input Shift Register Content

Figure 52. AD5684R Input Shift Register Content

ADDRESS BITS

COMMAND BITS

DAC

D15 D14 D13 D12 D11 D10

DB23 (MSB)

DB0 (LSB)

DATA BITS

ADDRESS BITS

COMMAND BITS

DAC

D13 D12 D11 D10

DB23 (MSB)

DB0 (LSB)

DATA BITS

ADDRESS BITS

COMMAND BITS

DAC

D11 D10

DB23 (MSB)

DB0 (LSB)

DATA BITS

AD5686R датащи(PDF) 21 Page - Analog Devices

AD5686R датащи(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

датащи скачать

ссылки URL