MX8682

IXYS

POWER-ON RESET

The MX8682 contains a power-on reset circuit that resets all the internal flip-flops and initializes the

internal registers to zero. The MX8682 will reset if the voltage at terminal PWR drops below 3.2V to 3.8V.

SYNCHRONOUS SERIAL I/O

The MX8682 (slave) can communicate with a microcomputer (master) via a three wire plus chip select

serial interface. Chip select CS*, serial clock SCK, and serial data input SDI are output from the master

controller to the MX8682.

Serial data output SDO is driven by the MX8682 when selected by CS* = 0.

SDO is high impedance when CS* = 1.

SCK and SDI are don't care when CS* = 1.

SDI is captured by the rising edge of SCK.

SDO changes in response to the falling edge of SCK.

Read 12-bit data D[11:0] when SDI = logic 0

CS*

SCK

SDO

SDI

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D11

200 nS min

60 nS max

Write command timing:

(Bit Field A[2:0] , B[5:0], OTP Bit Zp)

CS*

SCK

SDI

B0

B1

B2

B3

B4

B5

A0

A1

A2

0

1

Zp

The write command SDI input bit pattern is internally latched at the rising edge of

CS* and takes effect at the end of the next A/D conversion following CS* rising.

20 nS min

The exponentially weighted moving average digital filter has a transfer function equivalent to a first order

low pass filter.

The I/O timing remains exactly the same when the filter is used. No decimation is performed.

Let T = Sample interval (the time from CS* falling edge to CS* falling edge). Then bandwidth = 1/(2*pi*T).

Also if W = Sample weighting, then the digital output = W*(current sample) + (1-W)*(previous value).

At power-on the previous value is initialized to zero. A programmed change in A[2:0] does not reset the

previous value. Therefore when using the filter, multiple samples must be taken at power-on or after

changing A[2:0] before the filtered output will be correct.

MX8682

4

03/03/08

Drawing No. 0868209

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