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Data Sheet

AD5766/AD5767

Rev. C | Page 29 of 43

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5766/AD5767 are 16-channel, 16-bit/12-bit, serial

input, voltage output DACs capable of providing multiple

output ranges with ±20 mA output current capability. The

available output voltage ranges are as follows:

•

−20 V to 0 V

•

−16 V to 0 V

•

−10 V to 0 V

•

−10 V to +6 V

•

−12 V to +14 V

•

−16 V to +10 V

•

±5 V

•

±10 V

The devices operate from four supply voltages: AVCC, AVDD,

AVSS, and VLOGIC. AVCC is the power supply input voltage for the

DACs and other low voltage circuitry, whereas AVDD and AVSS

are the positive and negative analog supplies for the output

amplifiers. The output amplifiers require +2 V of headroom and

−2 V of footroom to drive 20 mA with a minimum output

voltage error of less than 1 LSB. Table 9 shows the power supply

requirements for the selected output range. VLOGIC defines the

logic levels for the digital input and output signals.

Table 9. Power Supply Requirements for the Selected

Output Range

Range (V)

AVSS Maximum (V)

AVDD Minimum (V)

−20 to 0

−22

2.97

−16 to 0

−18

2.97

−10 to 0

−12

2.97

−10 to +6

−12

−12 to +14

−14

−16 to +10

−18

−5 to +5

−7

−10 to +10

−12

DAC ARCHITECTURE

The architecture of one DAC channel consists of a resistor

string DAC followed by an output buffer amplifier. The voltage

at the VREF pin provides the reference voltage for the all DAC

channels. Figure 68 shows a block diagram of the DAC

architecture.

INPUT

OUTPUT

BUFFER AMPLIFIER

REFERENCE

BUFFER

VOUTX

VREF

RESISTOR

STRING

DAC

Figure 68. DAC Architecture

The input coding to the DAC is straight binary, the ideal output

voltage is given by

MIN

OUT

Span













where:

Span is the full extent of the DAC output voltage range from the

minimum to the maximum limit.

D is the decimal equivalent of the binary code that is loaded to

the DAC register.

N is 4096 for the AD5767 (12-bit version), and 65536 for the

AD5766 (16-bit version).

VMIN is the lowest voltage of the span.

RESISTOR STRING

The resistor string section is shown in Figure 69. It is a

simplified resistor string structure, each of Value R. The digital

code loaded to the DAC register determines at which node on

the string the voltage is connected to be fed into the output

amplifier. The voltage is tapped off by closing one of the

switches connecting the string to the amplifier. Because a string

of resistors is used, the DAC is guaranteed to be monotonic.

TO OUTPUT

AMPLIFIER

Figure 69. Resistor String

POWER-ON RESET (POR)

The AD5766/AD5767 contain a POR circuit that controls the

output voltage during power-up. The AD5766/AD5767 outputs

are clamped to ground at power-up and remain powered up at

this level until a valid write sequence is made to the span register

to configure the output range of the DAC. At power-on, the

dither functionality is also enabled.

A software executable reset function resets the DAC to the

power-up state. Command 0111 is reserved for this reset

function (see Table 30). A minimum time is required between a

reset and a successful write (see the timing characteristics in

Table 4). Figure 70 shows the programming sequence to follow

to configure the AD5766/AD5767 upon power-on.

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