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AD5766/AD5767

Data Sheet

Rev. C | Page 40 of 43

APPLICATIONS INFORMATION

DITHER CONFIGURATION

The AD5766/AD5767 contain two dither input pins to allow dither

tone signals to be coupled to any of the 16 DAC output channels.

Operate the AD5766/AD5767 using the dither functionality to

minimize the transient amplitude seen on the DAC outputs when

the dither functionality is enabled or disabled. The recommended

configuration of the dither functionality is as follows:

After the AD5766/AD5767 power up, the input dither

signals must be configured by writing to the dither scale

Configure the AD5766/AD5767 in normal operating mode

before applying dither by programming the span register.

Write to the apply N0 or N1 dither signal to DACs register

to couple the N0/N1 input dither signals to any DAC

output, VOUTx.

Enabling the dither feature on a channel can increase its

sensitivity to digital feedthrough.

THERMAL CONSIDERATIONS

Up to ±20 mA can be sourced from each channel on the

AD5766/AD5767; thus, it is important to understand the effects

of power dissipation on the package and its effects on junction

temperature. The internal junction temperature must not

exceed 150°C. The AD5766/AD5767 are packaged in a 49-ball,

4 mm × 4mm WLCSP and a 40-lead 6 mm × 6 mm LFCSP

package. The thermal impedance, θJA, is specified in the

Absolute Maximum Ratings section. It is important that the

device is not operated under conditions that cause the junction

temperature to exceed the maximum temperature specified in

the Absolute Maximum Ratings section.

The Thermal Calculation Example (WLCSP) section details

how to calculate the die temperature and maximum permitted

ambient temperature. The quiescent current of the AVDD, AVSS,

AVCC, and VLOGIC pins must also be included in the calculation

of the junction temperature. These calculations use the typical

supply currents specified in Table 1.

Thermal Calculation Example (WLCSP)

For this thermal calculation example, all 16 channels are

enabled with the ±10 V output voltage range used. Each channel

is drawing 2 mA for a +1V output voltage.

AVDD = Span + 2 V = 12 V

AVSS = Span − 2 V = −12 V

AVCC = VLOGIC = 3.3 V

where Span is the output voltage range, ±10 V.

The current required to supply 16 channels (output power) is

2 mA × 16 = 32 mA

The power required on the AVDD rail for the AD5766/AD5767

to supply the 16 channels and 6 mA typical supply current is

12 V × (32 mA + 6 mA) = 0.456 W

Next, add power dissipated by the AVSS, AVCC, and VLOGIC rails

(input power) as follows:

0.456 W + (−12 V × −9 mA) + (3.3 V × 8.3 mA) + (3.3 V ×

0.02 μA) = 0.59 W

To calculate the power dissipated by the AD5766/AD5767, use

the following equation:

PDISS = Input Power − Output Power

For example,

0.59 W − (32 mA × 1 V) = 0.558 W

Then, calculate the die temperature,

0.558 W × 53°C/W = 29.57°C

Using the following equation to calculate the maximum

permitted ambient temperature:

TA MAX = TJ MAX − Die Temperature

For example,

150°C − 29.57° = 120°C

The θJA specification assumes that proper layout and grounding

techniques are followed to minimize power dissipation, as

outlined in the Layout Guidelines section

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5766/AD5767 is via a

serial bus that uses a standard protocol compatible with DSPs

and microcontrollers. The communications channel requires a

4-wire serial interface consisting of a clock signal, a data input

signal, a data output signal, and a synchronization signal. The

device requires a 24-bit data-word with data valid on the falling

edge of SCLK.

AD5766/AD5767 TO SPI INTERFACE

The SPI interface of the AD5766/AD5767 is designed to be easily

connected to industry-standard DSPs and microcontrollers.

Figure 74 shows the AD5766/AD5767 connected to the Analog

Devices, Inc., ADSP-BF531 Blackfin® DSP. The Blackfin has an

integrated SPI port that can be connected directly to the SPI

pins of the AD5766/AD5767.

ADSP-BF531

AD5766/AD5767

SYNC

SPISELx

SCLK

SCK

DIN

MOSI

SDO

MISO

RESET

PF8

Figure 74. ADSP-BF531 SPI Interface

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