AD9735BBCZ datasheet(55/72 Pages) AD

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Data Sheet

AD9734/AD9735/AD9736

Rev. B | Page 55 of 72

SYNCHRONIZATION TIMING

When more than one AD973x must be synchronized or when

a constant group delay must be maintained, the internal

controllers cannot be used. If the FIFO is enabled, the delay

between multiple AD973x devices is unknown. If the

DATACLK_OUT from multiple devices is used, there is an

uncertainty of two DACCLK periods because the initial phase

of DATACLK_OUT with respect to DACCLK cannot be

controlled. This means one DAC must be used to provide

DATACLK_OUT for all synchronized DACs and all timing

must be externally managed. The following timing information

allows system timing to be calculated so that multiple AD973xs

can be synchronized.

DATACLK_OUT changes relative to the rising edge of

DACCLK+ and is delayed, as shown in Figure 101. Because

DACCLK is divided by 2 to create DATACLK_OUT, the phase

of DATACLK_OUT can be 0° or 180°. There is no way to

predict or control this relationship. It can be different after each

power cycle and is not affected by hardware or software resets.

tDDCO

DACCLK

DATACLK_OUT

Figure 101. DACCLK to DATACLK_OUT Delay

The incoming data is de-interleaved internally as shown in

Figure 78. In Figure 78, DBU (upper) and DBL (lower) represent

the de-interleaved data paths. Each edge of DATACLK_IN

latches an incoming sample in two alternating registers. The

DATACLK_IN to data setup and hold definitions are illustrated

in Figure 102. All the data input must be valid during the setup-

and-hold period. External skew effectively increases the setup

and hold times that the data source must meet.

DATACLK_IN

OR DATACLK_OUT

DATA_IN

tDH

tDSU

Figure 102. Standard Definitions for DATACLK_IN or DATACLK_OUT to

Data Setup and Hold, SD = 0

While correct DATA_IN vs. DATACLK_IN timing is critical,

the transition of the incoming data to the DACCLK domain is

equally critical. By referencing the incoming DATA and

DATACLK_IN timing to the DATACLK_OUT signal, some

timing uncertainty can be removed. The DATACLK_OUT

timing very closely tracks the timing of the DACCLK-

controlled registers. Any variation in the path delay affects both

paths in almost the same way. If DATACLK_OUT is not used,

the full DACCLK to DATACLK_OUT path variation reduces

the external timing margin. Figure 101 shows a simplified view

of the internal clocking scheme with the relevant delay paths.

The internal architecture is interleaved such that each phase has

twice as long to make the transition across the clock domains.

This results in an extremely narrow window where the

incoming data must be held stable.

Table 28 shows the timing parameters for Figure 101 and

Figure 102. These parameters were measured for a sample of

five devices from five silicon lots. Worst-case fast and slow skew

lots were included in addition to the nominal (or average) lot.

The typical −40°C to typical +85°C spread illustrates the

variability with temperature for a single lot. Adding in lot-to-lot

variation with the fast and slow lots indicates the worst-case

spread in timing.

The timing varies such that all of the parameters move in the

same direction. For example, if the DATACLK_IN to data setup

time is fast, the hold time is similarly fast. The DACCLK to

DATACLK_OUT delay and the DATACLK_OUT to data setup

and hold is also at the fast end of the range.

Note that the polarities of setup-and-hold values in Table 28

conform to the standard convention of setup time occurring

prior to the latching edge and hold time occurring after the

latching edge, as shown in Figure 102.

Table 28. AD973x Clock and Data Timing Parameters

Symbol and Definition

Fast −40°C

Typ −40°C

All +25°C

Typ +85°C

Slow +85°C

Unit

tDDCO − DACCLK to DATACLK_OUT Delay

+1650

+1800

+1890

+2050

+2350

tDCISU − DATACLK_IN to DATA Setup

−100

−120

−150

−170

−220

tDCIH − DATACLK_IN to DATA Hold

+210

+220

+240

+280

+360

tDISU − DATACLK_OUT to DATA Setup

+1310

+1440

+1611

+1710

+1970

tDIH − DATACLK_OUT to DATA Hold

−1250

−1360

−1548

−1640

−1890

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