S29AL032D datasheet(13/69 Pages) SPANSION

13 / 69 page

June 13, 2005 S29AL032D_00_A3

S29AL032D

Ad vance

Info rmat i o n

Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated

through the internal command register. The command register itself does not occupy any addres-

sable memory location. The register is composed of latches that store the commands, along with

the address and data information needed to execute the command. The contents of the register

serve as inputs to the internal state machine. The state machine outputs dictate the function of

the device. Table 1 lists the device bus operations, the inputs and control levels they require, and

the resulting output. The following subsections describe each of these operations in further detail.

Table 1. S29AL032D Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT

= Data Out

Notes:

1. When the ACC pin is at VHH, the device enters the accelerated program mode. See

2. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).

3. The sector protect and sector unprotect functions may also be implemented via programming equipment.

4. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector

protection depends on whether they were last protected or unprotected. If WP#/ACC = VHH, all sectors are unprotected.

5. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.

6. Models 03, 04 only

Word/Byte Configuration (Models 03, 04 Only)

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word

configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0

are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–

DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and

the DQ15 pin is used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is

the power control and selects the device. OE# is the output control and gates array data to the

output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs

array data in words or bytes.

Operation

CE#

OE# WE#

RESET#

WP#(Note 6)/

ACC

Addresses

(Note 3)

DQ0–

DQ7

DQ8–DQ15 (Note 6)

BYTE#

= VIH

BYTE# = VIL

Read

L/H

AIN

DOUT

DQ8–DQ14 =

High-Z, DQ15 =

A-1

Write (Note 1)

(Note 4)

AIN

(Note 5) (Note 5)

Accelerated Program

(Note 6)

VHH

AIN

(Note 5) (Note 5)

Standby

VCC ±

0.3 V

VCC ±

0.3 V

High-Z

Output Disable

L/H

High-Z

Reset

L/H

High-Z

Sector Protect (Note 3)

VID

L/H

SA, A6 = L,

A1 = H, A0 = L

(Note 5)

Sector Unprotect

(Note 3)

VID

(Note 4)

SA, A6 = H,

A1 = H, A0 = L

(Note 5)

Temporary Sector

Unprotect

VID

(Note 4)

AIN

(Note 5) (Note 5)

High-Z

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