AM6548 datasheet(135/299 Pages) TI1

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Note 6

SPRSP08_ELCH_04

Note 7

Note 8

VDDA_ADC_MCU, VDDA_LDO_WKUP, VDDA_POR_WKUP,

VDDS0_WKUP , VDDS1_WKUP , VDDS2_WKUP , VDDS0 ,

VDDS1 ,VDDS2 , VDDS3 , VDDS4 , VDDS5 , VDDS6 ,

VDDS7 , VDDS8 , VDDA_1P8_CSI0, VDDA_1P8_OLDI0,

VDDA_1P8_SERDES0, VDDA_MCU, VDDA_PLL_CORE,

VDDA_PLL0_DDR, VDDA_PLL1_DDR, VDDA_PLL_DSS,

VDDA_PLL_MPU0, VDDA_PLL_MPU1, VDDA_PLL_PER0,

VDDA_SRAM_CORE0, VDDA_SRAM_CORE1, VDDA_SRAM_MPU0,

VDDA_SRAM_MPU1, VDDA_WKUP, VDDS_OSC1

(2)

VDDA_3P3_IOLDO_WKUP,

VDDA_3P3_SDIO, VDDA_3P3_USB

VDDA_3P3_IOLDO0, VDDA_3P3_IOLDO1,

VDDS_DDR

WKUP_OSC0_XI, WKUP_OSC0_XO

RESETz, MCU_RESETz

RESETSTATz, MCU_RESETSTATz

WKUP_LFOSC0_XI, WKUP_LFOSC0_XO

(optional)

(3)

OSC1_XI, OSC1_XO

(optional)

(9)

PORz_OUT, MCU_PORz_OUT

MCU_BYP_POR

(5)

PORz, MCU_PORz

(4)

VDDSHV0_WKUP,VDDSHV1_WKUP, VDDSHV2_WKUP,

VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4,

VDDSHV5, VDDSHV6, VDDSHV7, VDDSHV8

VDD_MPU0, VDD_MPU1

VDD_CORE, VDD_DLL_MMC0, VDD_DLL_MMC1

VDD_MCU

VDD_WKUP0, VDD_WKUP1

Note 11

135

AM6548, AM6528, AM6546

AM6526, AM6527

www.ti.com

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

(9) OSC1 crystal and square-wave clock sources are disabled until software configures the oscillator. Software should enable oscillator after

PORz_OUT, MCU_PORz_OUT reset release.

(10) If WKUP LDO is used to power the WKUP domain, connect CAP_VDD_WKUP pin to VDD_WKUP0/1 pin. VDD_WKUP0/1 will start

ramping after VDDA_LDO_WKUP reaches a certain threshold. If WKUP LDO is bypassed, connect VDD_WKUP0/1 with VDD_MCU.

Figure 5-4 describes the Power-Up Sequencing using External Power-on-reset (POR), bypassing on-chip

POR circuit of the device.

Figure 5-4. Power-Up Sequencing using External Power-on-reset (POR), bypassing on-chip POR circuit

(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.

(2) The VDDS[2:0]_WKUP, VDDS[8:0] are sourced from the same 1.8 V VDDSHV[2:0]_WKUP, VDDSHV[8:0] supply. If

VDDSHV[2:0]_WKUP, VDDSHV[8:0] is configured as 3.3 V, VDDS[2:0]_WKUP, VDDS[8:0] should be sourced from the internal IO bias

LDO.

(3) WKUP_LFOSC0 crystal clock source is disabled until software configures the oscillator and should be enabled after PORz, MCU_PORz

reset release. WKUP_LFOSC0 square-wave clock source is not dependent on PORz, MCU_PORz.

(4) PORz should be pulled to VDDSHV0. MCU_PORz should be pulled to VDDSHV0_WKUP.

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