FEDL2201-01

1Semiconductor

ML2201–XXX

7/20

TIMING DIAGRAMS

Timing Diagram at Powering On

V

DD

PDWN

t

RST

t

PDH

ST

PI

Reset

Power Down

NOTE: The LSI’s reset operation can be performed by using a level input combination of

PDWN = “L”,

ST = “L” and PI = “H”. After powering on, the initial reset operation is required at the above timing.

Timing Diagram at Powering Up and Standby State

PDWN

AOUT

1/2 I

AOUT

t

DAR

t

DAF

Timing Diagram for Playback

PDWN

ST

PI

......

t

PDSS

t

SPS

AOUT

t

SPH

t

SAS

t

PW

t

PC