FEDL2201-01

1Semiconductor

ML2201–XXX

6/20

AC Characteristics

V

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Clock Oscillation Duty Cycle

f

DUTY

—

405060

%

Reset Input Time after Powering Up

t

RST

—10

—

—

µs

PDWN Hold Time after Reset Input

t

PDH

—10

—

—

µs

D/A Converter Transit Time

(Pop-Noise Canceller Work Time)

Note *1

t

—

606468

ms

PDWN – ST Setup Time

t

PDSS

—1

—

—

µs

ST – PI Setup Time

t

SPS

—1

—

—

µs

PI Pulse Width

t

PW

—

0.35

—

2000

µs

PI Cycle Time

t

PC

—

0.7

—

4000

µs

ST – PI Hold Time

t

SPH

—1

—

—

µs

ST – AOUT Setup Time

Note *2

t

SAS

At f

—

1050

µs

Phrase Stop Time

Note *2

t

DPS

At f

—

700

µs

Silence Time between Phrases

Note *2

t

BLN

At f

—

700

µs

Stop

ST Pulse Width

t

SSW

—

0.35

—

2000

µs

Phrase

ST – Phrase ST Pulse Duration

Note *2

t

PP

At f

1050

—

—

µs

Phrase

ST – Stop ST Pulse Duration

Note *2

t

PS

At f

1050

—

—

µs

Stop

ST – Phrase ST Pulse Duration

Note *2

t

SP

At f

500

—

—

µs

Sampling Frequency

Note *3

f

SAM

—

3.9

—

28.0

kHz

Note *1:

The value changes in proportion to the external clock frequency, f

Note *2:

The value changes in proportion to the sampling frequency, f

Note *3: The sampling frequency is determined by the external clock frequency, f

factor that is selected for each phrase.