AD9548BCPZ datasheet(60/111 Pages) AD

60 / 111 page

AD9548

Data Sheet

The register addresses and defaults are hexadecimal values. Use the default value when writing to registers and/or bits marked as unused.

Register addresses that are not listed in Table 36 are not used, and writing to those registers has no effect. The user should write the

default value to sections of registers marked reserved. In the Opt (Option) column, A = autoclear; E = inaccessible to the EEPROM;

L = live register (input/output update not required); R = read only; S = buffered register (update synchronous with serial port clock); and

C = buffered register (update synchronous with SYSCLK/32). See the Input/Output Programming Registers section for details.

Table 36.

Addr

Opt1

Name

Def

Serial Port Control and Part Identification

0x0000

L, E

SPI control

Uni-

directional

LSB first/

Inc Addr

Soft reset

Long

instruction

Unused

0x10

0x0000

Dup

I2C control

Unused

Soft reset

Unused

0x00

0x0001

L E

Reserved

Unused

0x0002

R, L

Reserved

Silicon revision number

0xC6

0x0003

R, L

Device ID

0x48

0x0004

L,E

Readback

Unused

Read buffer

0x00

0x0005

L, A,

I/O update

Unused

I/O update

0x00

System Clock (SYSCLK)

0x0100

External

loop filter

enable

Charge

pump

mode

(auto/

man)

Charge pump current [2:0]

Lock detect

timer

disable

Lock detect divider [1:0]

0x18

0x0101

N-divider [7:0]

0x28

0x0102

Unused

M-divider

reset

M-divider [1:0]

2×frequency

multiplier

enable

PLL enable

SYSCLK reference select

[1:0]

0x45

0x0103

Nom SYSCLK

period

Nominal system clock period (femtoseconds) [15:0]

[1 ns @ 1 ppm accuracy]

0x40

0x0104

0x42

0x0105

Unused

Nominal system clock period [20:16]

0x0F

0x0106

System clock

stability

System clock stability period (milliseconds) [15:0]

0x01

0x0107

0x00

0x0108

Unused

System clock stability period (milliseconds) [19:16]

0x00

General Configuration

0x0200

M0 in/out

M0 function [6:0]

0x00

0x0201

M1 in/out

M1 function [6:0]

0x00

0x0202

M2 in/out

M2 function [6:0]

0x00

0x0203

M3 in/out

M3 function [6:0]

0x00

0x0204

M4 in/out

M4 function [6:0]

0x00

0x0205

M5 in/out

M5 function [6:0]

0x00

0x0206

M6 in/out

M6 function [6:0]

0x00

0x0207

M7 in/out

M7 function [6:0]

0x00

0x0208

IRQ pin

output mode

Unused

IRQ pin output mode [1:0]

0x00

0x0209

IRQ mask

Unused

SYSCLK

unlocked

SYSCLK

locked

Unused

SYSCLK Cal

complete

SYSCLK Cal

started

0x00

0x020A

Unused

Distribution

sync

Watchdog

timer

EEPROM

fault

EEPROM

complete

0x00

0x020B

Switching

Closed

Free-run

Holdover

Freq

unlocked

Freq

locked

Phase

unlocked

Phase

locked

0x00

0x020C

Unused

History

updated

Frequency

unclamped

Frequency

clamped

Phase slew

unlimited

Phase slew

limited

0x00

0x020D

Ref AA

new profile

Ref AA

validated

Ref AA fault

cleared

Ref AA fault

Ref A

new profile

Ref A

validated

Ref A

fault

cleared

Ref A

fault

0x00

0x020E

Ref BB

new profile

Ref BB

validated

Ref BB

fault

cleared

Ref BB

fault

Ref B

new profile

Ref B

validated

Ref B

fault

cleared

Ref B

fault

0x00

0x020F

Ref CC

new profile

Ref CC

validated

Ref CC

fault

cleared

Ref CC

fault

Ref C

new profile

Ref C

validated

Ref C

fault

cleared

Ref C

fault

0x00

Rev. G | Page 60 of 111

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