 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
AD9547BCPZ датащи(PDF) 44 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9547BCPZ датащи(HTML) 44 Page - Analog Devices |
|
|
44 / 106 page  AD9547 Data Sheet STATUS AND CONTROL MULTIFUNCTION PINS (M0 TO M7) The AD9547 has eight digital CMOS I/O pins (M0 to M7) that are configurable for a variety of uses. The function of these pins is programmable via the register map. Each pin can control or moni- tor an assortment of internal functions, based on the contents of Register 0x0200 to Register 0x0207. To monitor an internal function with a multifunction pin, write a Logic 1 to the MSB of the register associated with the desired multifunction pin. The value of the seven LSBs of the register defines the control function, as shown in Table 25. Table 25. Multifunction Pin Output Functions (D7 = 1) D[6:0] Value Output Function Source Proxy 0 Static Logic 0 1 Static Logic 1 2 System clock divided by 32 3 Watchdog timer output 4 EEPROM upload in progress Register 0x0D00, Bit 0 5 EEPROM download in progress Register 0x0D00, Bit 1 6 EEPROM fault detected Register 0x0D00, Bit 2 7 SYSCLK PLL lock detected Register 0x0D01, Bit 0 8 SYSCLK PLL calibration in progress Register 0x0D01, Bit 1 9 Unused Unused 10 Unused Unused 11 SYSCLK PLL stable Register 0x0D01, Bit 4 12 to 15 Unused Unused 16 DPLL free running Register 0x0D0A, Bit 0 17 DPLL active Register 0x0D0A, Bit 1 18 DPLL in holdover Register 0x0D0A, Bit 2 19 DPLL in reference switchover Register 0x0D0A, Bit 3 20 Active reference: phase master Register 0x0D0A, Bit 6 21 DPLL phase locked Register 0x0D0A, Bit 4 22 DPLL frequency locked Register 0x0D0A, Bit 5 23 DPLL phase slew limited Register 0x0D0A, Bit 7 24 DPLL frequency clamped Register 0x0D0B, Bit 7 25 Tuning word history available Register 0x0D0B, Bit 6 26 Tuning word history updated Register 0x0D05, Bit 4 27 to 31 Unused Unused 32 Reference A fault Register 0x0D0C, Bit 2 33 Reference AA fault Register 0x0D0D, Bit 2 34 Reference B fault Register 0x0D0E, Bit 2 35 Reference BB fault Register 0x0D0F, Bit 2 36 to 47 Unused Unused 48 Reference A valid Register 0x0D0C, Bit 3 49 Reference AA valid Register 0x0D0D, Bit 3 50 Reference B valid Register 0x0D0E, Bit 3 51 Reference BB valid Register 0x0D0F, Bit 3 52 to 63 Unused Unused 64 Reference A active reference Register 0x0D0B, Bits[1:0] 65 Reference AA active reference Register 0x0D0B, Bits[1:0} 66 Reference B active reference Register 0x0D0B, Bits[1:0] 67 Reference BB active reference Register 0x0D0B, Bits[1:0] 68 to 79 Unused Unused 80 Clock distribution sync pulse Register 0x0D03, Bit 3 81 to 127 Unused To control an internal function with a multifunction pin, write a Logic 0 to the most significant bit of the register associated with the desired multifunction pin. The monitored function depends on the value of the seven least significant bits of the register, as shown in Table 26. Note that the default setting is M0 through M7 configured as inputs and the input function set to unused (the first entry in Table 26). Table 26. Multifunction Pin Input Functions (D7 = 0) D[6:0] Value Input Function Destination Proxy 0 Unused (default) Unused 1 I/O update Register 0x0005, Bit 0 2 Full power-down Register 0x0A00, Bit 0 3 Watchdog reset Register 0x0A03, Bit 0 4 IRQ reset Register 0x0A03, Bit 1 5 Tuning word history reset Register 0x0A03, Bit 2 6 to 15 Unused Unused 16 Holdover Register 0x0A01, Bit 6 17 Free run Register 0x0A01, Bit 5 18 Reset incremental phase offset Register 0x0A0C, Bit 2 19 Increment incremental phase offset Register 0x0A0C, Bit 0 20 Decrement incremental phase offset Register 0x0A0C, Bit 1 21 to 31 Unused Unused 32 Override Reference Monitor A Register 0x0A0F, Bit 0 33 Override Reference Monitor AA Register 0x0A0F, Bit 1 34 Override Reference Monitor B Register 0x0A0F, Bit 2 35 Override Reference Monitor BB Register 0x0A0F, Bit 3 36 to 47 Unused Unused 48 Force Validation Timeout A Register 0x0A0E, Bit 0 49 Force Validation Timeout AA Register 0x0A0E, Bit 1 50 Force Validation Timeout B Register 0x0A0E, Bit 2 51 Force Validation Timeout BB Register 0x0A0E, Bit 3 52 to 63 Unused Unused 64 Enable OUT0 Register 0x0401, Bit 0 65 Enable OUT1 Register 0x0401, Bit 1 66, 67 Unused Unused 68 Enable OUT0, OUT1 Register 0x0401, Bits[1:0] 69 Sync clock distribution outputs Register 0x0A02, Bit 1 70 to 127 Unused Unused If more than one multifunction pin operates on the same control signal, then internal priority logic ensures that only one multi- function pin serves as the signal source. The selected pin is the one with the lowest numeric suffix. For example, if both M3 and M7 operate on the same control signal, M3 is used as the signal source and the redundant pin is ignored. Rev. G | Page 44 of 106 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
