AD9547 datasheet(40/106 Pages) AD

40 / 106 page

AD9547

Data Sheet

Rev. G | Page 40 of 106

SYNC

CONTROL

ENABLEn/MODEn

SYNC SOURCE

CLKINP

OUT1P

OUT1N

OUT1

OUT0

CLKINN

OUT_RSET

OUT0P

OUT0N

Figure 47. Clock Distribution

Clock Input (CLKINx)

The clock input handles input signals from a variety of logic

families (assuming proper terminations and sufficient voltage

swing). It also handles sine wave input signals such as those

delivered by the DAC reconstruction filter. Its default operating

frequency range is 62.5 MHz to 500 MHz.

Super-Nyquist Operation

Typically, the maximum usable frequency at the DAC output is

about 45% of the system clock frequency. However, because it is

a sampled DAC, its output spectrum contains Nyquist images.

Of particular interest are the images appearing in the first Nyquist

zone (50% to 100% of the system clock frequency). Super-Nyquist

operation takes advantage of these higher frequencies, but this

implies that the CLKINx input operates in excess of 500 MHz,

which is outside its default operating limits.

The CLKINx receiver actually consists of two separate receivers:

the default receiver and an optional high frequency receiver,

which handles input signals up to 800 MHz. To select the high

frequency receiver, write a Logic 1 to Register 0x0400, Bit4.

Super-Nyquist operation requires a band-pass filter at the DAC

output instead of the usual low-pass reconstruction filter. Super-

Nyquist operation is viable as long as the image frequency does

not exceed the 800 MHz input range of the receiver. Furthermore,

to provide acceptable jitter performance, which is a consideration

for image signals with low amplitude, the signal at the CLKINx

inputs must meet the minimum slew rate requirements.

Clock Dividers

The output clock distribution dividers are referred to as Q0 and Q1,

corresponding to the OUT0 and OUT1 output channels, respec-

tively. Each divider is programmable with 30 bits of division depth.

The actual divide ratio is one more than the programmed register

value; therefore, a register value of 3, for example, results in a

divide ratio of 4. Thus, each divider offers a range of divide ratios

from 1 to 230 (1 to 1,073,741,824).

With an even divide ratio, the output signal always exhibits a

50% duty cycle. When the clock divider is bypassed (a divide

ratio of 1), the output duty cycle is the same as the input duty

cycle. Odd output divide ratios (excluding 1) exhibit automatic

duty cycle correction given by

Cycle

Duty

Output







where:

N (which must be an odd number) is the divide ratio.

X is the normalized fraction of the high portion of the input period

(that is, 0 < X < 1).

For example, if N = 5 and the input duty cycle is 20% (X = 0.2),

then the output duty cycle is 44%. Note that, when the user

programs an output as noninverting, then the device adjusts the

falling edge timing to accomplish the duty cycle correction.

Conversely, the device adjusts the rising edge timing for an

inverted output.

Output Power-Down

Each output channel offers independent control of power-down

functionality via the distribution settings register (Address 0x0400).

Each output channel has a dedicated power-down bit for powering

down the output driver. However, if both channels are powered

down, the entire distribution output enters a deep sleep mode.

Even though each channel has a channel power-down control

signal, it may sometimes be desirable to power down an output

driver while maintaining the divider’s synchronization with the

other channel dividers. This is accomplished by either of the

following methods:



In CMOS mode, use the divider output enable control bit

to stall an output. This provides power savings while main-

taining dc drive at the output.



In LVDS/LVPECL mode, place the output in tristate mode

(this works in CMOS mode as well).

Output Enable

Each output channel offers independent control of enable/

disable functionality using the distribution enable register

(Address 0x0401). The distribution outputs use synchronization

logic to control enable/disable activity to avoid the production

of runt pulses and to ensure that outputs with the same divide

ratios become active/inactive in unison.

Output Mode

The user has independent control of the operating mode of each of

the two output channels via the distribution channel modes register

(Address 0x0404 and Address 0x0405). The operating mode

control includes



Logic family and pin functionality



Output drive strength



Output polarity

The three LSBs of both distribution channel mode registers com-

prise the mode bits. The mode value selects the desired logic family

and pin functionality of an output channel, as listed in Table 24.

AD9547 датащи(PDF) 40 Page - Analog Devices

AD9547 датащи(HTML) 40 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL