AD9547 datasheet(39/106 Pages) AD

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Data Sheet

AD9547

Bits[5:3]). The charge pump current varies from 125 µA to 1 mA

in 125 µA steps. The default setting is 500 µA.

SYSCLK PLL Loop Filter

The AD9547 has an internal second-order loop filter that estab-

lishes the loop dynamics for input signals between 12.5 MHz and

100 MHz. By default, the device uses the internal loop filter.

However, an external loop filter option is available by setting

the external loop filter enable bit (Register 0x0100, Bit 7). This

bit bypasses the internal loop filter and allows the device to use

an externally connected second-order loop filter, as shown in

Figure 46.

SYSCLK_VREG

AD9547

SYSCLK_LF

Figure 46. External Loop Filter Schematic

To determine the external loop filter components, the user decides

on the desired open loop bandwidth (fOL) and phase margin (Φ).

These parameters allow calculation of the loop filter components,

as follows:

R1 =

( )













sin

VCO

C1 =

)

(

)

tan(

VCO

C2 =













−

)

cos(

)

sin(

)

(

VCO

where:

KVCO = 7 × 107 V/ns (typical).

ICP is the programmed charge pump current (amperes).

N is the programmed feedback divider value.

fOL is the desired open-loop bandwidth (Hz).

Φ is the desired phase margin (radians).

For example, assuming that N = 40, ICP = 0.5 mA, fOL = 400 kHz,

and Φ = 50°, then the loop filter calculations yield R1 = 3.31 kΩ,

C1 = 330 pF, and C2 = 50.4 pF.

System Clock Period

Many of the user programmable parameters of the AD9547 have

absolute time units. To make this possible, the AD9547 requires

a priori knowledge of the period of the system clock. To accom-

modate this requirement, the user programs the 21-bit nominal

system clock period in the nominal SYSCLK period register

(Address 0x0103 to Address 0x0105). The contents of this register

reflect the actual period of the system clock in units of femto-

seconds (fs). The user must program this register properly to

ensure proper operation of the device because many of its

subsystems rely on this value.

System Clock Stability Timer

The system clock stability timer, located in Register 0x0106 to

seconds (ms). If the programmed timer value is 0, the timer

immediately indicates that it has timed out. If the programmed

timer value is nonzero and the SYSCLK PLL is enabled, the timer

starts timing when the SYSCLK PLL lock detector indicates lock

and times out after the prescribed period. However, when the user

disables the SYSCLK PLL, the timer ignores the SYSCLK PLL

lock detector and starts timing the instant that the SYSCLK PLL

is disabled. The user can monitor the status of the stability timer

at Register 0x0D01, Bit 4, via the multifunction pins or via the

IRQ pin.

Note that the system clock stability timer must be programmed

before the SYSCLK PLL is either activated or disabled.

SYSCLK PLL Calibration

When using the SYSCLK PLL, it is necessary to calibrate the

LC-VCO to ensure that the PLL can remain locked to the system

clock input signal. Assuming the presence of either an external

SYSCLK input signal or a crystal resonator, the calibration process

executes after the user sets and then clears the calibrate system

clock bit in the cal/sync register (Register 0x0A02, Bit 0). During

the calibration process, the device calibrates the VCO amplitude

and frequency. The status of the system clock calibration process

is user accessible via the system clock status register (Register

0x0D01, Bit 1). It is also available via the IRQ monitor register

(Bit 1 of Register 0x0D02), provided that the status bit is enabled

via the IRQ mask register (Register 0x0209 and Register 0x0210).

When the calibration sequence is complete, the SYSCLK PLL

eventually attains a lock condition, at which point the system

clock stability timer begins its countdown sequence. Expiration

of the timer indicates that the SYSCLK PLL is stable, which is

reflected in the system clock status register (Register 0x0D01, Bit 4).

Note that the monitors/detectors associated with the input

references (REF A/REF AA and REF B/REF BB) are internally

disabled until the SYSCLK PLL indicates that it is stable.

CLOCK DISTRIBUTION

The clock distribution block of the AD9547 provides an integrated

solution for generating multiple clock outputs based on frequency

dividing the DPLL output. The distribution output consists of

two channels (OUT0 and OUT1). Each channel has a dedicated

divider and output driver section, as shown in Figure 47.

Rev. G | Page 39 of 106

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