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AD9540 датащи(PDF) 2 Page - Analog Devices

номер детали AD9540
подробное описание детали  655 MHz Low Jitter Clock Generator
PDF  32 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9540 датащи(HTML) 2 Page - Analog Devices

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AD9540
Data Sheet
Rev. C | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Overview............................................................................. 3
Specifications..................................................................................... 4
Loop Measurement Conditions.................................................. 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Typical Application Circuits.......................................................... 17
Application Circuit Descriptions ............................................. 18
Theory of Operation ...................................................................... 19
PLL Circuitry .............................................................................. 19
CML Driver................................................................................. 19
DDS and DAC............................................................................. 20
Modes of Operation ....................................................................... 21
Selectable Clock Frequencies and Selectable Edge Delay..... 21
Synchronization Modes for Multiple Devices.............................. 21
Serial Port Operation ..................................................................... 22
Instruction Byte.......................................................................... 23
Serial Interface Port Pin Description....................................... 23
MSB/LSB Transfers .................................................................... 23
Register Map and Description...................................................... 24
Control Register Bit Descriptions............................................ 27
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
4/2018—Rev. B to Rev. C
Changes to Figure 3........................................................................ 10
Updated Outline Dimensions....................................................... 32
Changes to Ordering Guide .......................................................... 32
9/2016—Rev. A to Rev. B
Change to Features ........................................................................... 1
Updated Outline Dimensions....................................................... 32
Changes to Ordering Guide .......................................................... 32
2/2006—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
Changes to Applications Section.....................................................1
Changes to Functional Block Diagram...........................................1
Changes to Table 1.............................................................................4
Changes to Typical Application Circuits Section....................... 17
Updates to Ordering Guide........................................................... 32
7/2004—Revision 0: Initial Version



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