AD9540 datasheet(18/32 Pages) AD

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AD9540

Data Sheet

Rev. C | Page 18 of 32

REFIN

CLK2

CP_OUT

DDS

÷R

VCO

AD9540

LPF

DAC

÷N

CML

DRIVER

2.5GHz

TONE

8-LEVEL FSK

(FC = 100MHz)

BPF

25MHz

CRYSTAL

Figure 36. ISM Band Modulator (LO & Baseband Generation)

APPLICATION CIRCUIT DESCRIPTIONS

Dual Clock Configuration

In this loop, M = 1, N = 16, and R = 4. The DDS (direct digital

synthesizer) tuning word is also equal to ¼, so that the

frequency of CLOCK1’ equals the frequency of CLOCK 1.

Phase adjustments in the DDS provide 14-bit programmable

rising edge delay capability of CLOCK1’ with respect to

CLOCK1 (see Figure 32).

Optical Networking Clock

This is the AD9540 configured as an optical networking clock.

The loop can be used to generate a 622 MHz clock for OC12.

The DDS can be programmed to output 8 kHz to serve as a base

reference for other circuits in the subsystem (see Figure 33).

Fractional-Divider Loop This loop offers the precise frequency

division (48-bit) of the DDS in the feedback path as well as the

frequency sweeping capability of the DDS. Programming the

DDS to sweep from 24 MHz to 25 MHz sweeps the output of

the VCO from 2.7 GHz to 2.6 GHz. The reference in this case is

a simple crystal (see Figure 34).

Direct Upconversion

The AD9540 is configured to use the DDS as a precision

reference to the PLL. Since the VCO is <655 MHz, it can be fed

straight into the phase frequency detector feedback.

LO and Baseband Modulation Generation

Using the AD9540 PLL section to generate LO and the DDS

portion to generate a modulated baseband, this circuit uses an

external mixer to perform some simple modulation at RF ISM

band frequencies (see Figure 36).

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