SSC2005SC datasheet(15/19 Pages) SANKEN

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SSC2005SC

SSC2005SC-DS Rev.1.1

SANKEN ELECTRIC CO.,LTD.

Feb. 06, 2015

 Output Capacitor: C2

Apply proper design margin to accommodate the

ripple current, the ripple voltage and the temperature

rise. Use of high ripple current and low impedance

types, designed for switch-mode power supplies, is

recommended, depending on their purposes.

C2 is calculated by both Equation (12) and (14), and

is selected the large value of them.

1) Given the C2 ripple voltage VOUTRIPPLE (VPP) (10 VPP

for example), C2 is expressed as follows:

)

(

OUT

LINE

OUT









(F)

(12)

where,

fLINE :Line frequency (Hz)

IOUT :Output current (A)

The C2 voltage is expressed by Equation (13).

When the output ripple is high, the VC2 voltage may

reach to Overvoltage Protection voltage, VOVP, in near

the maximum value of VC2, or input current waveform

may be distorted due to the stop of the boost operation

in near the minmum value of VC2. It is necessary to

select large C2 value or change the setting of output

voltage (boost voltage).

)

(

OUT





(V)

(13)

2) Given the output hold time as tHOLD (s), C2 is

expressed as follows:











2

)

MIN

(

OUT

HOLD

OUT







(F)

(14)

where,

tHOLD

: Output hold time (s)

VOUT(MIN) : Minmum output voltage of C2 during

output hold (V)

: Efficiency

9.3

PCB Trace Layout and Component

Placement

Since the PCB circuit trace design and the component

layout significantly affects operation, EMI noise, and

power dissipation, the high frequency PCB trace should

be low impedance with small loop and wide trace.

In addition, the ground traces affect radiated EMI noise,

and wide, short traces should be taken into account.

Figure 9-4 shows the circuit design example. Figure

9-5 shows the PCB pattern layout example around the

IC.

(1) Main Circuit Trace

This is the main trace containing switching currents,

and thus it should be as wide trace and small loop as

possible.

(2) Control Ground Trace Layout

Since the operation of the IC may be affected from

the large current of the main trace that flows in

control ground trace, the control ground trace should

be separated from main trace and connected at a

single point grounding of point A in Figure 9-4 as

close to the RCS as possible.

(3) RCS Trace Layout

RCS should be placed as close as possible to the

Source pin and the CS pin.

The peripheral components of the CS pin should be

connected by dedicated pattern from root of RCS.

The connection between the power ground of the

main trace and the IC ground should be at a single

point ground which is close to the base of RCS.

(4) Peripheral Component of the IC

The components for control connected to the IC

should be placed as close as possible to the IC, and

should be connected as short as possible to the each

pin.

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