AD9543 datasheet(23/66 Pages) AD

23 / 66 page

Data Sheet

AD9543

Rev. 0 | Page 23 of 66

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

OUT0AP

Output

HCSL, LVDS,

CML, CMOS

PLL0 Output 0A.

OUT0AN

Output

HCSL, LVDS,

CML, CMOS

PLL0 Complementary Output 0A.

OUT0BP

Output

HCSL, LVDS,

CML, CMOS

PLL0 Output 0B.

OUT0BN

Output

HCSL, LVDS,

CML, CMOS

PLL0 Complementary Output 0B.

16, 21, 44

DNC

No Connect

Do Not Connect. Leave these pins floating.

OUT0CP

Output

HCSL, LVDS,

CML, CMOS

PLL0 Output 0C.

OUT0CN

Output

HCSL, LVDS,

CML, CMOS

PLL0 Complementary Output 0C.

OUT1BP

Output

HCSL, LVDS,

CML, CMOS

PLL1 Output 1B.

OUT1BN

Output

HCSL, LVDS,

CML, CMOS

PLL1 Complementary Output 1B.

OUT1AP

Output

HCSL, LVDS,

CML, CMOS

PLL1 Output 1A.

OUT1AN

Input/

Output

HCSL, LVDS,

CML, CMOS

PLL1 Complementary Output 1A.

LF1

Input/

output

Loop filter

for APLL1

Loop Filter Node for APLL1. Connect a 3.9 nF capacitor from this pin to

Pin 30 (LDO1).

LDO1

Input

LDO bypass

APLL1 Loop Filter Voltage Regulator. Connect a 0.1 μF capacitor from

this pin to ground. This pin is the ac ground reference for the

integrated APLL1 loop filter.

32, 33, 35, 36, 37

M0, M1, M2, M3, M4

Input/

output

CMOS

Configurable Input/Output Pins. These are status and control pins.

Changes to the VDDIOB supply voltage affect the VIH and VOH values for

these pins. M3 and M4 have internal 100 kΩ pull-down resistors. M0,

M1, and M2 do not have internal resistors.

VDDIOB

Input

Power

Mx Pin Power Supply. This power supply powers the digital section

that controls the M0 to M4 pins. Valid supply voltages are 1.8 V, 2.5 V,

or 3.3 V. The VDDIOB pin can be connected to the VDD supply bus if

1.8 V operation is desired.

REFB

Input

1.8 V single-

ended or

differential

input

Reference B Input. This internally biased input is typically ac-coupled;

when configured in this manner, it can accept any differential signal

with a single-ended swing up to the VDD power supply. If dc-coupled,

the input can be LVDS or single-ended 1.8 V CMOS.

REFBB

Input

1.8 V single-

ended or

differential

input

Reference BB Input or Complementary Reference B Input. If REFB is in

differential mode, the REFB complementary signal is on this pin. No

connection is necessary to this pin if REFB is a single-ended input and

REFBB is not used.

XOA

Input

Differential

input

System Clock Input. XOA contains internal dc biasing and is ac-coupled

with a 0.01 µF capacitor except when using a crystal. When a crystal is

used, connect the crystal across XOA and XOB. A single-ended CMOS

input is also an option, but it can produce spurious spectral content

when the duty cycle is not 50%. When using XOA as a single-ended

input, connect a 0.1 μF capacitor from XOB to ground.

XOB

Input

Differential

input

Complementary System Clock Input. Complementary signal to XOA.

XOB contains internal dc biasing and is ac-coupled with a 0.1 µF

capacitor except when using a crystal. When a crystal is used, connect

the crystal across XOA and XOB.

REFAA

Input

1.8 V single-

ended or

differential

input

Reference AA input or Complementary REFA Input. If REFA is in

differential mode, the REFA complementary signal is on this pin. No

connection is necessary to this pin if REFA is a single-ended input and

REFAA is not used. If dc-coupled, the input is single-ended 1.8 V CMOS.

REFA

Input

1.8 V single-

ended or

differential

Reference A Input. This internally biased input is typically ac-coupled;

when configured in this manner, it can accept any differential signal

with a single-ended swing up to the VDD power supply. If dc-coupled,

AD9543 датащи(PDF) 23 Page - Analog Devices

AD9543 датащи(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

датащи скачать

ссылки URL