AD9530BCPZ datasheet(27/41 Pages) AD

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Data Sheet

AD9530

Rev. 0 | Page 27 of 41

APPLICATIONS INFORMATION

POWER SUPPLY RECOMMENDATIONS

The AD9530 only requires 2.5 V for operation, but proper isolation

between power domains is beneficial for performance. Figure 31

shows the recommended Analog Devices power solutions for

the best possible performance of the AD9530. These devices are

also featured on the evaluation board.

ADM7154

LDO

2.5V: VDD OUT

AND VDD REF

(PIN 3, PIN 7, PIN 31,

PIN 35, PIN 41, PIN 45)

ADP151

LDO

2.5V: VDD DIGITAL

(PIN 12)

ADP7158

(RECOMMENDED)

ADP1741

LDO

ADP2386

BUCK

REGULATOR

2.5V: VDD RTWO

(PINS 20 TO 23)

INPUT

3.4V

Figure 31. Power Supply Recommendation

USING THE AD9530 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Any high speed ADC is extremely sensitive to the quality of the

sampling clock of the AD9530. An ADC can be thought of as a

sampling mixer, and any noise, distortion, or time jitter on the

clock is combined with the desired signal at the analog-to-digital

output. Clock integrity requirements scale with the analog input

frequency and resolution, with higher analog input frequency

applications at ≥14-bit resolution being the most stringent. The

theoretical SNR of an ADC is limited by the ADC resolution and

the jitter on the sampling clock. Considering an ideal ADC of

infinite resolution, where the step size and quantization error

can be ignored, the available SNR can be expressed

approximately by















SNR



log

(dB)

where:

fA is the highest analog frequency being digitized.

tJ is the rms jitter on the sampling clock.

Figure 32 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

fA (MHz)

100

110

= 100

= 200

= 400

= 1p

= 2p

= 10p

SNR = 20log

πfAtJ

Figure 32. SNR and ENOB vs. Analog Input Frequency (fA)

For more information, see the AN-756 Application Note,

Sampled Systems and the Effects of Clock Phase Noise and Jitter,

and the AN-501 Application Note, Aperture Uncertainty and

ADC System Performance.

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. Distributing a single-ended clock on a noisy PCB can

result in coupled noise on the sampling clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.

The differential CML outputs of the AD9530 enable clock

solutions that maximize converter SNR performance.

Consider the input requirements of the ADC (differential or single-

ended, logic level termination) when selecting the best clocking/

converter solution.

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