AD9530BCPZ datasheet(7/41 Pages) AD

7 / 41 page

Data Sheet

AD9530

Rev. 0 | Page 7 of 41

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DUTY CYCLE

Duty cycle bounds are set by pulse width high and pulse

width low

Pulse Width

Low

600

High

600

PLL CHARACTERISTICS

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

RTWO

Frequency Range

5.11

5.4

GHz

VCO Gain (KVCO)

180

MHz/V

PHASE FREQUENCY DETECTOR (PFD)

PFD Input Frequency

800

MHz

Antibacklash pulse width disabled (Register 0x026, Bit 1 = 0)

500

MHz

Antibacklash pulse width enabled (Register 0x026, Bit 1 = 1)

CHARGE PUMP (CP)

Sink/Source Current (ICP)

0.05

2.6

Table 56)

LOOP FILTER

External Loop Filter Capacitor

3.2

µF

Maximum value for the C2 capacitor in Figure 16; using a loop filter

capacitor value larger than the maximum may affect device

functionality

POWER-ON RESET (POR) TIMER

Internal Wait Time

sec

Minimum wait time implemented before issuing the first RTWO

calibration after a POR

PLL DIGITAL LOCK DETECT SPECIFICATIONS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PLL DIGITAL LOCK DETECT WINDOW1

Signal available at the LD pin and in Register 0x01F, Bit 2

Lock Threshold

±0.020

±300

ppm

Lock threshold is selected by Register 0x01D, Bits[3:1], which is

the threshold for transitioning from unlock to lock and vice

versa

1 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the lock detector update interval (see Table 48).

CLOCK OUTPUTS (INTERNAL TERMINATION DISABLED) SPECIFICATIONS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CML MODE

All outputs are externally terminated with 50 Ω to VDD

800 mV

Output Frequency

5.725

2700

MHz

Rise Time/Fall Time (20% to 80%)

107

Duty Cycle

Any Mx divider, output divider ≠ 1

Mx divider = 2, output divider = 1

Mx divider = 2.5, output divider = 1

Mx divider = 3, output divider = 1

Output Differential Voltage, Magnitude

600

845

1090

Voltage difference between the output pins; output driver is

static; in normal operation, the peak-to-peak amplitude is

approximately 2× this value if measured with a differential probe

Common-Mode Output Voltage

1.82

2.075

2.32

Measured with output driver static

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