AD9523BCPZ datasheet(58/60 Pages) AD

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AD9523

Data Sheet

Rev. D | Page 58 of 60

Address

Bits

Bit Name

Description

0x232

[7:5]

Reserved

Reserved.

Enable STATUS_EEPROM

on STATUS0 pin

Enables the EEPROM status on the STATUS0 pin.

1: enable status.

STATUS1 pin divider

enable

Enables a divide-by-4 on the STATUS1 pin, allowing dynamic signals to be viewed at a lower

frequency (such as the PFD input clocks). Not to be used with dc states on the status pins,

which occur when the settings of Register 0x231[5:0] are in the range of 000000 to 001111.

1: enabled.

0: disabled.

STATUS0 pin divider

enable

Enables a divide-by-4 on the STATUS0 pin, allowing dynamic signals to be viewed at a lower

frequency (such as the PFD input clocks). Not to be used with dc states on the status pins,

which occur when the settings of Register 0x230[5:0] are in the range of 000000 to 001111.

1: enable.

0: disable.

Reserved

Reserved.

Sync dividers

(manual control)

Set bit to put dividers in sync; clear bit to release. Functions like SYNC pin low.

1: sync.

0: normal.

Table 56. Power-Down Control

Address

Bits

Bit Name

Description

0x233

[7:3]

Reserved

Reserved.

PLL1 power-down

1: power-down (default).

0: normal operation.

PLL2 power-down

1: power-down (default).

0: normal operation.

Distribution power-

down

Powers down the distribution.

1: power-down (default).

0: normal operation.

Table 57. Update All Registers

Address

Bits

Bit Name

Description

0x234

[7:1]

Reserved

Reserved.

IO_UPDATE

This bit must be set to 1 to transfer the contents of the buffer registers into the active registers,

which happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have

to be set back to 0.

1 (self-clearing): update all active registers to the contents of the buffer registers.

EEPROM Buffer (Address 0xA00 to Address 0xA16)

Table 58. EEPROM Buffer Segment

Address

Bits

Bit Name

Description

0xA00

0xA16

[7:0]

EEPROM Buffer

Segment Register 1 to

EEPROM Buffer

Segment Register 23

The EEPROM buffer segment section stores the starting address and number of bytes that are

to be stored and read back to and from the EEPROM. Because the register space is noncontiguous,

the EEPROM controller needs to know the starting address and number of bytes in the register

space to store and retrieve from the EEPROM. In addition, there are special instructions for the

EEPROM controller: operational codes (that is, IO_UPDATE and end-of-data) that are also stored in

the EEPROM buffer segment. The on-chip default setting of the EEPROM buffer segment

registers is designed such that all registers are transferred to/from the EEPROM, and an IO_UPDATE

is issued after the transfer (see the Programming the EEPROM Buffer Segment section).

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