Data Sheet

HMC6832

Rev. C | Page 13 of 23

0

50

100

150

200

250

300

350

400

450

500

0

1

2

3

4

5

6

7

8

LOADED BANKS

86Ω

150Ω

Figure 10. 3.3 V Current Consumption vs. Loaded Banks

0

50

100

150

200

250

300

350

0

1

2

3

4

5

6

7

8

LOADED BANKS

86Ω

150Ω

Figure 11. 2.5 V Current Consumption vs. Loaded Banks

–5

0

1

2

3

4

–4

–3

–2

–1

5

0

1

2

3

4

5

6

7

OUTPUT CHANNEL

Figure 12. Skew of Outputs Relative to Average Delay, Characterized at 1.25 GHz;

Effects of Customer Evaluation Board Skew and Loss Are De-Embedded

–25

–20

–15

–10

–5

0

–22

–17

–12

–7

–2

INPUT POWER (dBm)

LVDS

, 100Ω

LVPECL

, 150Ω

LVPECL

, 86Ω

Figure 13. 1.25 GHz Fundamental Differential Output Power vs. Differential

Input Power, Uncorrected for Impedance Mismatch

–6

–5

–4

–3

–2

–1

0

1

10M

100M

1G

10G

CARRIER FREQUENCY (Hz)

BOARD LOSS

200Ω TERMINATION

150Ω TERMINATION

86Ω TERMINATION

Figure 14. LVPECL Evaluation Board Output Trace Loss and Distortion from

Impedance Mismatch vs. Carrier Frequency

10M

100M

1G

10G

CARRIER FREQUENCY (Hz)

–20

–15

–10

–5

0

5

10

+25°C

–40°C

+85°C

Figure 15. LVPECL 2.5 V Differential Output Power vs. Carrier Frequency for

Various Temperatures, 0 dBm Input, Network Analyzer Gating Used to

Remove Input and Output Impedance Mismatch and Board Loss