TDA9550 datasheet(14/125 Pages) PHILIPS

14 / 125 page

2000 Jun 22

Philips Semiconductors

Tentative Device Speciﬁcation

TV signal processor-Teletext decoder with

embedded

µ-Controller

TDA955X/6X/8X PS/N1 series

bytes are grouped into 4 banks of 8 registers, the next 16 bytes above the register banks form a block of bit addressable

memory space. The upper 128 bytes are not allocated for any special area or functions.

SFR MEMORY

The Special Function Register (SFR) space is used for port latches, counters/timers, peripheral control, data capture and

display. These registers can only be accessed by direct addressing. Sixteen of the addresses in the SFR space are both

bit and byte addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. A summary of the SFR

map in address order is shown in Table 2.

ADD

R/W

Names

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

80H

R/W

Reserved

P0<6>

P0<5>

Reserved

81H

R/W

SP<7>

SP<6>

SP<5>

SP<4>

SP<3>

SP<2>

SP<1>

SP<0>

82H

R/W

DPL

DPL<7>

DPL<6>

DPL<5>

DPL<4>

DPL<3>

DPL<2>

DPL<1>

DPL<0>

83H

R/W

DPH

DPH<7>

DPH<6>

DPH<5>

DPH<4>

DPH<3>

DPH<2>

DPH<1>

DPH<0>

84H

R/W

IEN1

-------

ET2

85H

R/W

IP1

-------

PT2

87H

R/W

PCON

ARD

RFI

WLE

GF1

GF0

IDL

88H

R/W

TCON

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

89H

R/W

TMOD

GATE

C/TM1

GATE

C/TM1

8AH

R/W

TL0

TL0<7>

TL0<6>

TL0<5>

TL0<4>

TL0<3>

TL0<2>

TL0<1>

TL0<0>

8BH

R/W

TL1

TL1<7>

TL1<6>

TL1<5>

TL1<4>

TL1<3>

TL1<2>

TL1<1>

TL1<0>

8CH

R/W

TH0

TH0<7>

TH0<6>

TH0<5>

TH0<4>

TH0<3>

TH0<2>

TH0<1>

TH0<0>

8DH

R/W

TH1

TH1<7>

TH1<6>

TH1<5>

TH1<4>

TH1<3>

TH1<2>

TH1<1>

TH1<0>

90H

R/W

P1<7>

P1<6>

Reserved

P1<3>

P1<2>

P1<1>

P1<0>

91H

R/W

TP2L

TP2L<7>

TP2L<6>

TP2L<5>

TP2L<4>

TP2L<3>

TP2L<2>

TP2L<1>

TP2L<0>

Table 2

SFR Map

Bank Select

Bits in PSW

00H

08H

10H

18H

20H

07H

0FH

17H

1FH

2FH

11 = BANK3

7FH

10 = BANK2

01 = BANK1

00 = BANK0

Fig.7 Lower 128 Bytes of Internal RAM

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