LPC84X datasheet(12/97 Pages) NXP

12 / 97 page

LPC84x

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Product data sheet

Rev. 1.7 — 27 February 2018

12 of 97

NXP Semiconductors

LPC84x

32-bit Arm Cortex-M0+ microcontroller

RESET/PIO0_5

[7]

I; PU

RESET — External reset input: A LOW-going pulse

(minimum 20 ns to maximum 50 ns) on this pin

resets the device, causing I/O ports and peripherals

to take on their default states, and processor

execution to begin at address 0.

This pin triggers a wake-up from deep power-down

mode. If the part must wake up from deep

power-down mode via the RESET pin, do not assign

any movable function to this pin and must be

externally pulled HIGH before entering deep

power-down mode. The RESET pin can be left

unconnected or be used as a GPIO or for any

movable function if an external RESET function is

not needed.

PIO0_5 — General-purpose port 0 input/output 5.

PIO0_6/ADC_1/

ACMPVREF

[10] I; PU

PIO0_6 — General-purpose port 0 input/output 6.

ADC_1 — ADC input 1.

ACMPVREF — Alternate reference voltage for the

analog comparator.

PIO0_7/ADC_0

[2]

I; PU

PIO0_7 — General-purpose port 0 input/output 7.

ADC_0 — ADC input 0.

PIO0_8/XTALIN

[8]

I; PU

PIO0_8 — General-purpose port 0 input/output 8.

XTALIN — Input to the oscillator circuit and internal

clock generator circuits. Input voltage must not

exceed 1.95 V in slave mode. See Section 14.2.2

“XTAL input”.

PIO0_9/XTALOUT

[8]

I; PU

PIO0_9 — General-purpose port 0 input/output 9.

XTALOUT — Output from the oscillator circuit.

PIO0_10/I2C0_SCL 17

[6]

Inactive I; F

PIO0_10 — General-purpose port 0 input/output 10

(open-drain).

I2C0_SCL — Open-drain I2C-bus clock input/output.

High-current sink if I2C Fast-mode Plus is selected in

the I/O configuration register.

PIO0_11/I2C0_SDA 16

[6]

Inactive I; F

PIO0_11 — General-purpose port 0 input/output 11

(open-drain).

I2C0_SDA — Open-drain I2C-bus data input/output.

High-current sink if I2C Fast-mode Plus is selected in

the I/O configuration register.

PIO0_12

[4]

I; PU

PIO0_12 — General-purpose port 0 input/output 12.

ISP entry pin. A LOW level on this pin during reset

starts the ISP command handler.

PIO0_13/ADC_10

[2]

I; PU

PIO0_13 — General-purpose port 0 input/output 13.

ADC_10 — ADC input 10.

Table 4.

Pin description

Symbol

Reset

state[1]

Type Description

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