LPC84X datasheet(21/97 Pages) NXP

21 / 97 page

LPC84x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.7 — 27 February 2018

21 of 97

NXP Semiconductors

LPC84x

32-bit Arm Cortex-M0+ microcontroller

8.10 Switch Matrix (SWM)

The switch matrix controls the function of each digital or mixed analog/digital pin in a

highly flexible way by allowing to connect many functions, for example, the USART, SPI,

SCTimer/PWM, CTimer, and I2C functions to any pin that is not power or ground. These

functions are called movable functions and are listed in Table 5.

Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can

be enabled or disabled through the switch matrix. These functions are called fixed-pin

functions and cannot move to other pins. The fixed-pin functions are listed in Table 4. If a

fixed-pin function is disabled, any other movable function can be assigned to this pin.

8.11 Fast General-Purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs

can be set or cleared in one write operation.

LPC84x use accelerated GPIO functions:

• GPIO registers are on the Arm Cortex-M0+ IO bus for fastest possible single-cycle I/O

timing, allowing GPIO toggling with rates of up to 15 MHz.

• An entire port value can be written in one instruction.

• Mask, set, and clear operations are supported for the entire port.

All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the

switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be

moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and

RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default.

8.11.1 Features

• Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation.

• Direction control of individual bits.

• All I/O default to GPIO inputs with internal pull-up resistors enabled after reset -

except for the I2C-bus true open-drain pins PIO0_10 and PIO0_11.

• Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed

through the IOCON block for each GPIO pin (see Figure 9).

• Direction (input/output) can be set and cleared individually.

• Pin direction bits can be toggled.

8.12 Pin interrupt/pattern match engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight

external interrupts connected to the NVIC.

The pattern match engine can be used, with software, to create complex state machines

based on pin inputs.

LPC84X датащи(PDF) 21 Page - NXP Semiconductors

LPC84X датащи(HTML) 21 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

датащи скачать

ссылки URL