WM8950 datasheet(30/52 Pages) WOLFSON

номер детали	WM8950

подробное описание детали	ADC WITH MICROPHONE INPUT AND PROGRAMMABLE DIGITAL FILTERS

PDF	52 Pages

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производитель	WOLFSON [Wolfson Microelectronics plc]

домашняя страница	http://www.wolfsonmicro.com

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WM8950

Preliminary Technical Data

PTD Rev 2.1 June 2005

Figure 15 Right Justified Audio Interface (assuming n-bit word length)

In I

2S mode, the MSB is available on the second rising edge of BCLK following a FRAME transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

Figure 16 I

2S Audio Interface (assuming n-bit word length)

In DSP/PCM mode, the left channel MSB is available on either the 1

st (mode B) or 2nd (mode A)

rising edge of BCLK (selectable by FRAMEP) following a rising edge of FRAME. Right channel data

immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,

there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

In device master mode, the LRC output will resemble the frame pulse shown in Figure 17 and Figure

18. In device slave mode, Figure 19 and Figure 20, it is possible to use any length of frame pulse

less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period

before the rising edge of the next frame pulse.

Figure 17 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)

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