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M58BW032BT датащи(PDF) 19 Page - STMicroelectronics |
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M58BW032BT датащи(HTML) 19 Page - STMicroelectronics |
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19 / 60 page ![]() 19/60 M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 6. Burst Configuration Register Note: 1. X latencies can be calculated as: (tAVQV – tLLKH + tKHQV) + tSYSTEM MARGIN < (X -1) tK. (X is an integer number from 4 to 8 and tK is the clock period), , where tLLKH is the value given by the master microcontroller timing specifications. 2. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tKHQV < Y tK. 3. tSYSTEM MARGIN is the time margin required for the calculation. Bit Description Value Description M15 Read Select 0 Synchronous Burst Read 1 Asynchronous Read (Default at power-up) M14 Standby Disable 0 Standby Mode Enabled (Default at power-up) 1 Standby Mode Disabled M13-M11 X-Latency (1) 001 3 010 4 011 5 100 6 101 7 110 8 M10 Reserved M9 Y-Latency (2) 0 One Burst Clock cycle 1 Two Burst Clock cycles M8 Valid Data Ready 0 R valid Low during valid Burst Clock edge 1 R valid Low one data cycle before valid Burst Clock edge M7-M4 Reserved M3 Wrapping 0Wrap 1No Wrap M2-M0 Burst Length 001 4 Double-Words 010 8 Double-Words 111 Continuous |
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