M58BW032BT datasheet(13/60 Pages) STMICROELECTRONICS

13 / 60 page

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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram and Table 1., Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A19). The Address Inputs

are used to select the cells to access in the mem-

ory array during Bus Read operations either to

read or to program data to. During Bus Write oper-

ations they control the commands sent to the

Command Interface of the internal state machine.

Chip Enable must be Low when selecting the ad-

dresses.

The address inputs are latched on the rising edge

of Latch Enable L or Burst Clock K, whichever oc-

curs first, in a read operation.The address inputs

are latched on the rising edge of Chip Enable,

Write Enable or Latch Enable, whichever occurs

first in a Write operation. The address latch is

transparent when Latch Enable is Low, VIL. The

address is internally latched in an Erase or Pro-

gram operation.

Data Inputs/Outputs (DQ0-DQ31). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation, or are used

to input the data during a program operation. Dur-

ing Bus Write operations they represent the com-

mands sent to the Command Interface of the

internal state machine. When used to input data or

Write commands they are latched on the rising

edge of Write Enable or Chip Enable, whichever

occurs first.

When Chip Enable and Output Enable are both

Low, VIL, and Output Disable is at VIH, the data

bus outputs data from the memory array, the Elec-

tronic Signature, the Block Protection Configura-

tion Register, the CFI Information or the contents

of Burst Configuration Register or Status Register.

The data bus is high impedance when the device

is deselected with Chip Enable at VIH, Output En-

able at VIH, Output Disable at VIL or Reset/Power-

Down at VIL. The Status Register content is output

on DQ0-DQ7 and DQ8-DQ31 are at VIL.

Chip Enable (E). The Chip Enable, E, input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. Chip Enable, E, at

VIH deselects the memory and reduces the power

consumption to the Standby level.

Output Enable (G). The Output Enable, G, gates

the outputs through the data output buffers during

a read operation, when Output Disable GD is at

VIH. When Output Enable G is at VIH, the outputs

are high impedance independently of Output Dis-

able.

Output Disable (GD). The Output Disable, GD,

deactivates the data output buffers. When Output

Disable, GD, is at VIH, the outputs are driven by

the Output Enable. When Output Disable, GD, is

at VIL, the outputs are high impedance indepen-

dently of Output Enable. The Output Disable pin

must be connected to an external pull-up resistor

as there is no internal pull-up resistor to drive the

pin.

Write Enable (W). The Write Enable, W, input

controls writing to the Command Interface, Input

Address and Data latches. Both addresses and

data can be latched on the rising edge of Write En-

able (also see Latch Enable, L).

Reset/Power-Down (RP). The

Reset/Power-

Down, RP, is used to apply a hardware reset to the

memory. A hardware reset is achieved by holding

Reset/Power-Down Low, VIL, for at least tPLPH.

Writing is inhibited to protect data, the Command

Interface and the Program/Erase Controller are re-

set. The Status Register information is cleared and

power consumption is reduced to the standby level

(IDD1). The device acts as deselected, that is the

data outputs are high impedance.

After Reset/Power-Down goes High, VIH, the

memory will be ready for Bus Read operations af-

ter a delay of tPHEL or Bus Write operations after

tPHWL.

If Reset/Power-Down goes Low, VIL, during a

Block Erase, a Program or a Tuning Protection

Program the operation is aborted, in a time of tPL-

RH maximum, and data is altered and may be cor-

rupted.

During Power-up power should be applied simulta-

neously to VDD and VDDQ(IN) with RP held at VIL.

When the supplies are stable RP is taken to VIH.

Output Enable, G, Chip Enable, E, and Write En-

able, W, should be held at VIH during power-up.

In an application, it is recommended to associate

Reset/Power-Down pin, RP, with the reset signal

of the microprocessor. Otherwise, if a reset opera-

tion occurs while the memory is performing an

erase or program operation, the memory may out-

put the Status Register information instead of be-

ing

initialized

the

default

Asynchronous

Random Read.

See Table 21 and Figure 17., Reset, Power-Down

and Power-up AC Waveform, for more details.

Program/Erase Enable (VPEN). The

Program./

Erase Enable input, VPEN, protects all blocks, pre-

venting Program and Erase operations from mod-

ifying the data. Program/Erase Enable must be

kept High (VIH) during all operations when the Pro-

gram/Erase Controller is active, otherwise the op-

eration is not guaranteed to succeed and data may

become corrupt.

Latch Enable (L). The Bus Interface can be con-

figured to latch the Address Inputs on the rising

edge of Latch Enable, L, for Asynchronous Latch

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