ADAU1977WBCPZ-R7 datasheet(26/68 Pages) AD

26 / 68 page

ADAU1977

Data Sheet

Rev. C | Page 26 of 68

TDM Mode

for the TDM mode. The TDM slot width, data width, and

channel assignment, as well as the pin used to output the data,

are programmable.

By default, serial data is output on the SDATAOUT1 pin;

however, the SDATA_SEL bit (Bit 7 of Register 0x06) can be

used to change the setting so that serial data is output from the

SDATAOUT2 pin.

The TDM mode supports 2, 4, 8, or 16 channels. The ADAU1977

outputs four channels of data in the assigned slots (Figure 29

shows the data slot assignments). During the unused slots, the

output pin goes high-Z so that the same data line can be shared

with other devices on the TDM bus.

The TDM port can be operated as either a master or a slave.

In master mode, the BCLK and LRCLK are output from the

ADAU1977, whereas in slave mode, the BCLK and LRCLK pins

are set to receive the clock from the master in the system.

Both the nonpulse and pulse modes are supported. In nonpulse

mode, the LRCLK signal is typically 50% of the duty cycle, whereas

in pulse mode, the LRCLK signal must be at least one BCLK wide

(see Figure 27 and Figure 28).

Figure 27. TDM Nonpulse Mode Audio Format

Figure 28. TDM Pulse Mode Audio Format

BCLK

LRCLK

SDATA I2S

SDATA LJ

CHANNEL 1

CHANNEL 2

CHANNEL N

CHANNEL 2

CHANNEL N

32/24/16 BCLKs

8 TO 32 BCLKs

32/24/16 BCLKs

SDATA I2S

CHANNEL 1

CHANNEL 2

CHANNEL N

24 OR 16 BCLKs

NOTES

1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS).

2. SDATA_FMT = 00 (I2S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT).

3. BCLK_EDGE = 0.

4. LRCLK_MODE = 0.

5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs).

BCLK

LRCLK

SDATA I2S

SDATA LJ

CHANNEL 1

CHANNEL 2

CHANNEL N

CHANNEL 2

CHANNEL N

32/24/16 BCLKs

8 TO 32 BCLKs

32/24/16 BCLKs

SDATA I2S

CHANNEL 1

CHANNEL 2

CHANNEL N

24 OR 16 BCLKs

NOTES

1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS)

2. SDATA_FMT = 00 (I2S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT)

3. BCLK_EDGE = 0

4. LRCLK_MODE = 1

5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs)

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