12

LTC2602/LTC2612/LTC2622

2602f

OPERATIO

Board Layout

The excellent load regulation and DC crosstalk perfor-

mance of these devices is achieved in part by keeping

“signal” and “power” grounds separated internally and by

reducing shared internal resistance.

The GND pin functions both as the node to which the

reference and output voltages are referred and as a return

path for power currents in the device. Because of this,

careful thought should be given to the grounding scheme

and board layout in order to ensure rated performance.

The PC board should have separate areas for the analog

and digital sections of the circuit. This keeps digital signals

away from sensitive analog signals and facilitates the use

of separate digital and analog ground planes which have

minimal capacitive and resistive interaction with each

other.

Digital and analog ground planes should be joined at only

one point, establishing a system star ground as close to

the device’s ground pin as possible. Ideally, the analog

ground plane should be located on the component side of

the board, and should be allowed to run under the part to

shield it from noise. Analog ground should be a continu-

ous and uninterrupted plane, except for necessary lead

pads and vias, with signal traces on another layer.

The GND pin of the part should be connected to analog

ground. Resistance from the GND pin to system star

ground should be as low as possible. Resistance here will

add directly to the effective DC output impedance of the

device (typically 0.050

Ω), and will degrade DC crosstalk.

Note that the LTC2602/LTC2612/LTC2622 are no more

susceptible to these effects than other parts of their type;

on the contrary, they allow layout-based performance

improvements to shine rather than limiting attainable

performance with excessive internal resistance.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is

limited to voltages within the supply range.

Since the analog outputs of the device cannot go below

ground, they may limit for the lowest codes as shown in

Figure 3b. Similarly, limiting can occur near full scale

full-scale error (FSE) is positive, the output for the highest

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting can

occur.