ZL2005P datasheet(21/41 Pages) RENESAS

21 / 41 page

ZL2005P

FN6849 Rev 3.00

Page 21 of 41

December 16, 2011

Figure 16. SYNC Pin Configurations

Configuration A: SYNC OUTPUT

When the SYNC pin is configured as an output (CFG

pin is tied HIGH), the device will operate from its inter-

nal oscillator and will drive the resulting internal oscilla-

tor signal (preset to 400 kHz) onto the SYNC pin so

other devices can be synchronized to it. The SYNC pin

will not be checked for an incoming clock signal while

in this configuration.

Configuration B: SYNC INPUT

When the SYNC pin is configured as an input (CFG pin

is tied LOW), the device will automatically check for a

clock signal on the SYNC pin each time EN is asserted.

The ZL2005P’s oscillator will then synchronize with the

rising edge of external clock.

The incoming clock signal must be in the range of 200

kHz to 1.4 MHz and must be stable when the enable pin

is asserted. The clock signal must also exhibit the neces-

sary performance requirements (see Table 3). In the

event of a loss of the external clock signal, the output

voltage may show transient over/undershoot.

If this happens, the ZL2005P will turn off the power

FETs (QH and QL in Figure 4) typically within 10

S.

Users are discouraged from removing an external SYNC

clock while the ZL2005P is operating with Enable

asserted.

Configuration C: SYNC AUTO DETECT

When the SYNC pin is configured in auto detect mode

(CFG pin is left OPEN), the device will automatically

check for a clock signal on the SYNC pin after enable is

asserted.

If a clock signal is present, The ZL2005P’s oscillator

will then synchronize the rising edge of the external

clock. Refer to SYNC INPUT description.

If no incoming clock signal is present, the ZL2005P will

configure the switching frequency according to the state

of the SYNC pin as listed in Table 16. In this mode, the

ZL2005P will only read the SYNC pin connection

during the start-up sequence. Changes to SYNC pin con-

nections will not affect fSW until the power (VDD) is

cycled off and on.

Table 16. Switching Frequency Selection

If the user wishes to run the ZL2005P at a frequency

other than those listed in Table 16, the switching fre-

quency can be set using an external resistor, RSYNC,

connected between SYNC and SGND using Table 17.

Logic

high

SYNC

200 kHz – 1.4 MHz

SYNC

200 kHz – 1.4 MHz

N/C

SYNC

200 kHz – 1.4 MHz

A) SYNC = output

B) SYNC = input

N/C

SYNC

RSYNC

N/C

SYNC

Logic

high

Logic

low

Open

C) SYNC = Auto Detect

SYNC Pin Setting

Frequency

LOW

200 kHz

OPEN

400 kHz

HIGH

1 MHz

Resistor

See Table 17

ZL2005P датащи(PDF) 21 Page - Renesas Technology Corp

ZL2005P датащи(HTML) 21 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

датащи скачать

ссылки URL