PIC16F505 datasheet(37/98 Pages) MICROCHIP

37 / 98 page

 2004 Microchip Technology Inc.

Preliminary

DS41236A-page 35

PIC12F508/509/16F505

6.1

Using Timer0 with an External

Clock

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock require-

ment is due to internal phase clock (TOSC) synchroniza-

tion. Also, there is a delay in the actual incrementing of

Timer0 after synchronization.

6.1.1

EXTERNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 6-4).

Therefore, it is necessary for T0CKI to be high for at

least 2 TOSC (and a small RC delay of 2 Tt0H) and low

for at least 2 TOSC (and a small RC delay of 2 Tt0H).

Refer to the electrical specification of the desired

device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler, so that the prescaler output is symmetrical.

For the external clock to meet the sampling require-

ment, the ripple counter must be taken into account.

Therefore, it is necessary for T0CKI to have a period of

at least 4 TOSC (and a small RC delay of 4 Tt0H) divided

by the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the

minimum pulse width requirement of Tt0H. Refer to

parameters 40, 41 and 42 in the electrical specification

of the desired device.

6.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 6-4 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 6-4:

TIMER0 TIMING WITH EXTERNAL CLOCK

Increment Timer0 (Q4)

External Clock Input or

Q1 Q2

Timer0

T0 + 1

T0 + 2

Small pulse

misses sampling

External Clock/Prescaler

Output After Sampling

(3)

Prescaler Output (2)

(1)

Note 1:

Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error

in measuring the interval between two edges on Timer0 input = ±4 TOSC max.

External clock if no prescaler selected; prescaler output otherwise.

The arrows indicate the points in time where sampling occurs.

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