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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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P89LPC912FDH датащи(PDF) 13 Page - NXP Semiconductors |
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P89LPC912FDH датащи(HTML) 13 Page - NXP Semiconductors |
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13 / 63 page  Philips Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 03 — 17 December 2004 13 of 63 9397 750 14468 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. P2.2 to P2.5 I/O Port 2: Port 2 is a 4-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 9.11.1 “Port configurations” and Table 13 “DC electrical characteristics” for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below: 1 I/O P2.2 — Port 2 bit 2. I/O MOSI — SPI master out slave in. When configured as master, this pin is output, when configured as slave, this pin is input. 14 I/O P2.3 — Port 2 bit 3. I/O MISO — SPI master in slave out. When configured as master, this pin is input, when configured as slave, this pin is output. 8 I/O P2.4 — Port 2 bit 4. I SS — SPI Slave select. 2 I/O P2.5 — Port 2 bit 5. I/O SPICLK — SPI clock. When configured as master, this pin is output, when configured as slave, this pin is input. VSS 4I Ground: 0 V reference. VDD 10 I Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. Table 5: P89LPC914 pin description…continued Symbol Pin Type Description |
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