FDMF3170 datasheet(13/21 Pages) ONSEMI

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FDMF3170

Rev. 1.2

Functional Description

The SPS FDMF3170 is a driver plus MOSFET module

optimized for the synchronous buck converter topology.

A PWM input signal is required to properly drive the

high-side and the low-side MOSFETs. The part is

capable of driving speed up to 1 MHz.

EN and UVLO

The SPS FDMF3170 is enabled by both EN pin input

signal and VCC / PVCC UVLO. Table 1 summarizes the

enable and disable logics. With EN low and Vcc UVLO,

SPS is fully shut down. If VCC is ready but EN is low,

SPS goes to sleep mode with very low quiescent

current, where only critical circuitry such as the

bandgap and general housekeeping circuitry are alive.

The part should also read fuses/program itself during

this state.

Table 1.

UVLO and Driver State

VCC

UVLO

PVCC

UVLO

Driver State

Full driver shutdown (GH,

GL=0), requires 40 µs for

startup

Partial driver shutdown

(GH, GL=0), requires 10 µs

for startup

Driver analog circuitry alive

but outputs forced into tri-

state (GH, GL=0)

Enabled

(GH/GL follow PWM)

Open/0 Disabled (GH, GL=0)

The FDMF3170 needs 40 µs time to go from fully

shutdown mode to power ready mode. The time is

10 µs from partial shutdown mode power ready. Before

power is ready, TMON pin is strongly pull low with a

 resistor. As a result, TMON pin can also be used

as a power ready indicator.

3-State PWM Input

The FDMF3170 incorporates a 3-state 3.3 V PWM input

gate drive design. The 3-state gate drive has both logic

HIGH and LOW levels, along with a 3-state shutdown

window. When the PWM input signal enters and

remains within the 3-state window for a defined hold-off

time (tD_HOLD-OFF), both GL and GH are pulled LOW.

This feature enables the gate drive to shut down both

high-side and low-side MOSFETs to support features

such as phase shedding, a common feature on multi-

phase voltage regulators.

Table 2.

Enable / PWM / 3-State / OFF# Logic

Enable

PWM

3-State

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