ISL6566 datasheet(18/30 Pages) RENESAS

18 / 30 page

ISL6566

FN9178 Rev 4.00

Page 18 of 30

Mar 9, 2006

2. The voltage on ENLL must be above 0.66V. The ENLL

input allows for power sequencing between the controller

bias voltage and another voltage rail. The enable

comparator holds the ISL6566 in shutdown until the

voltage at ENLL rises above 0.66V. The enable

comparator has 60mV of hysteresis to prevent bounce.

3. The driver bias voltage applied at the PVCC pins must

reach the internal power-on reset (POR) rising threshold.

In order for the ISL6566 to begin operation, PVCC1 is the

only pin that is required to have a voltage applied that

exceeds POR. However, for 2 or 3-phase operation

PVCC2 and PVCC3 must also exceed the POR

threshold. Hysteresis between the rising and falling

thresholds assure that once enabled, the ISL6566 will not

inadvertently turn off unless the PVCC bias voltage drops

substantially (see Electrical Specifications).

4. The VID code must not be 111111 or 111110 in VRM10

mode or 11111 in AMD Hammer or VRM9 modes. These

codes signal the controller that no load is present. The

controller will enter shut-down mode after receiving either

of these codes and will execute soft-start upon receiving

any other code. These codes can be used to enable or

disable the controller but it is not recommended. After

receiving one of these codes, the controller executes a

2-cycle delay before changing the overvoltage trip level to

the shut-down level and disabling PWM. Overvoltage

shutdown cannot be reset using one of these codes.

When each of these conditions is true, the controller

immediately begins the soft-start sequence.

SOFT-START

The soft-start function allows the converter to bring up the

output voltage in a controlled fashion, resulting in a linear

ramp-up. Following a delay of 16 PHASE clock cycles

between enabling the chip and the start of the ramp, the

output voltage progresses at a fixed rate of 12.5mV per each

16 PHASE clock cycles.

Thus, the soft-start period (not including the 16 PHASE clock

cycle delay) up to a given voltage, VDAC, can be

approximated by the following equation

where VDAC is the DAC-set VID voltage, and fS is the

switching frequency.

The ISL6566 also has the ability to start up into a pre-

charged output, without causing any unnecessary

disturbance. The FB pin is monitored during soft-start, and

should it be higher than the equivalent internal ramping

reference voltage, the output drives hold both MOSFETs off.

Once the internal ramping reference exceeds the FB pin

potential, the output drives are enabled, allowing the output

to ramp from the pre-charged level to the final level dictated

by the DAC setting. Should the output be pre-charged to a

level exceeding the DAC setting, the output drives are

enabled at the end of the soft-start period, leading to an

abrupt correction in the output voltage down to the DAC-set

level.

FIGURE 11. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (ENLL) FUNCTION

0.66V

EXTERNAL CIRCUIT

ISL6566 INTERNAL CIRCUIT

ENLL

+12V

POR

CIRCUIT

10.7k



1.40k



ENABLE

COMPARATOR

SOFT-START

AND

FAULT LOGIC

VCC

PVCC1

TSS

VDAC 1280



---------------------------------

(EQ. 13)

FIGURE 12. SOFT-START WAVEFORMS FOR ISL6566-BASED

MULTI-PHASE CONVERTER

ENLL (5V/DIV)

VOUT (0.5V/DIV)

GND>

OUTPUT PRECHARGED

BELOW DAC LEVEL

OUTPUT PRECHARGED

ABOVE DAC LEVEL

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