ISL6277

FN8270 Rev 1.00

Page 33 of 37

Mar 8, 2012

power train. Symmetrical layout allows heat to be dissipated

equally across all power trains. Keeping the distance between

the power train and the control IC short helps keep the gate drive

traces short. These drive signals include the LGATE, UGATE,

PGND, PHASE and BOOT.

When placing MOSFETs, try to keep the source of the upper

MOSFETs and the drain of the lower MOSFETs as close as

thermally possible (see Figure 33). Input high-frequency

capacitors should be placed close to the drain of the upper

MOSFETs and the source of the lower MOSFETs. Place the output

inductor and output capacitors between the MOSFETs and the

load. High-frequency output decoupling capacitors (ceramic)

should be placed as close as possible to the decoupling target

(microprocessor), making use of the shortest connection paths to

any internal planes. Place the components in such a way that the

area under the IC has less noise traces with high dV/dt and di/dt,

such as gate signals and phase node signals.

Table 14 shows layout considerations for the ISL6277 controller

by pin.

FIGURE 33. TYPICAL POWER COMPONENT PLACEMENT

INDUCTOR

VIAS TO

GROUND

PLANE

VIN

VOUT

PHASE

NODE

GND

OUTPUT

CAPACITORS

LOW-SIDE

MOSFETS

INPUT

CAPACITORS

SCHOTTKY

DIODE

HIGH-SIDE

MOSFETS

TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6277 CONTROLLER

ISL6277 PIN

SYMBOL

LAYOUT GUIDELINES

BOTTOM PAD

GND

Connect this ground pad to the ground plane through a low impedance path. A minimum of 5 vias are

recommended to connect this pad to the internal ground plane layers of the PCB

1

ISEN2_NB

Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN_NB, then through another capacitor (Cvsumn_nb)

to GND. Place Cisen capacitors as close as possible to the controller and keep the following loops small:

1. ISEN1_NB pin to ISEN2_NB pin

2. Any ISENx_NB pin to GND

2

NTC_NB

The NTC thermistor must be placed close to the thermal source that is monitored to determine Northbridge

thermal throttling. Placement at the hottest spot of the Northbridge VR is recommended. Additional standard

resistors in the resistor network on this pin should be placed near the IC.

3

IMON_NB

Place the IMON_NB resistor close to this pin and make keep a tight GND connection.

4

SVC

Use good signal integrity practices and follow AMD recommendations.

5

VR_HOT_L

Follow AMD recommendations. Placement of the pull-up resistor near the IC is recommended.

6

SVD

Use good signal integrity practices and follow AMD recommendations.

7

VDDIO

Use good signal integrity practices and follow AMD recommendations.

8

SVT

Use good signal integrity practices and follow AMD recommendations.

9

ENABLE

No special considerations.

10

PWROK

Use good signal integrity practices and follow AMD recommendations.

11

IMON

Place the IMON resistor close to this pin and make keep a tight GND connection.

12

NTC

The NTC thermistor must be placed close to the thermal source that is monitored to determine Core thermal

throttling. Placement at the hottest spot of the Core VR is recommended. Additional standard resistors in the

resistor network on this pin should be placed near the IC.